Secure MMIO Address Mapping for Confidential Accelerator Access
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Solution Overview
Problem
Current confidential computing architectures centered on CPUs fail to meet the security and efficiency requirements in heterogeneous computing scenarios, particularly in scenarios involving GPUs or NPUs, as they lack effective mechanisms to protect data confidentiality and integrity in such environments.
Innovation Solution
A device access method and apparatus that utilizes a secure world and a non-secure world to manage memory and accelerator access through memory-mapped input/output (MMIO) addresses, ensuring secure communication and resource allocation in a heterogeneous computing environment, including the use of session keys for encryption and decryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CPU-centered confidential computing architecture is used, then data security is improved, but computing efficiency and adaptability in heterogeneous computing scenarios deteriorate
Solution Approach 1:
The system divides computing tasks between secure world (for security-critical operations) and non-secure world (for performance-critical operations), allowing heterogeneous computing resources to be segmented and allocated according to their security and performance characteristics
Solution Approach 2:
A security manager acts as an intermediary between the secure world and non-secure world, managing memory space allocation, MMIO address mapping, and communication protocols to enable efficient heterogeneous computing while maintaining security boundaries
2Reliability
If a CPU-centered confidential computing architecture is used, then data confidentiality is improved, but adaptability to heterogeneous computing scenarios deteriorates
Solution Approach 1:
The secure world is designed with universal interfaces including MMIO address space for accelerator access, memory space grant mechanisms, and standardized communication protocols that enable it to work with various heterogeneous computing devices (GPUs, NPUs, FPGAs) while maintaining data confidentiality
Solution Approach 2:
The system introduces a new dimension of address space management by separating physical address space into secure and non-secure regions, enabling heterogeneous devices to access memory and accelerators through properly mapped MMIO addresses while maintaining security isolation
3Reliability
If memory space is allocated to secure world, then data protection is improved, but device complexity increases
Solution Approach 1:
The system performs preliminary actions by pre-defining secure and non-secure memory regions, pre-establishing MMIO address mappings, and pre-configuring security manager policies before computing tasks begin, thereby reducing runtime complexity and improving data protection
Solution Approach 2:
The system manages device complexity by dynamically adjusting memory space parameters, MMIO address mappings, and security policies based on the specific computing tasks and hardware configurations, allowing flexible resource allocation without overwhelming complexity
Data Source
AI summary
Embodiments of this application provide a device access method and apparatus. The method is applied to a first device. The first device includes a secure world and a non-secure world. The method includes: The first device receives first request information sent by a server, where the first request information is used to request the first device to determine a first memory address, and the first memory address corresponds to a first MMIO address in a secure world of the server; and the first device determines the first memory address in the secure world of the first device based on the first request information. According to the foregoing method, a data channel established between the server and the first device cannot be stolen by software in the non-secure world, so that a confidential computing requirement of a tenant in a heterogeneous computing architecture scenario is met.