Secure Module Token Processing for TEE CPU Efficiency

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Solution Overview

Problem

Data processing systems with Trusted Execution Environments (TEEs) face significant overhead due to the need to frequently switch between secure and non-secure modes, which limits CPU efficiency and task handling when performing operations that require access to secure assets.

Innovation Solution

A secure module is configured to process tokens for secure assets in both secure and non-secure modes, using rules to manage permissions and allow cross-domain operations, enabling the CPU to remain in non-secure mode during asset processing and reducing the need for frequent mode switches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the CPU switches to secure mode to process tokens requiring secure assets, then security is ensured, but operational overhead increases and CPU efficiency decreases

Engineering Contradiction:
ImprovesecurityVSAvoidCPU efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the token processing function into two parts: security verification (requiring secure mode) and asset processing (can be handled in non-secure mode by the secure module). This allows the CPU to remain in non-secure mode for most operations while only switching to secure mode for essential security verification, thereby reducing operational overhead while maintaining security.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the CPU switches to secure mode for secure operations, then secure assets are protected, but task handling capability deteriorates

Engineering Contradiction:
Improvesecure asset protectionVSAvoidtask handling capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent introduces a secure module as an intermediary between the CPU and secure assets. This secure module can process tokens in non-secure mode and only requires the CPU to switch to secure mode for final verification. This intermediary approach protects secure assets while allowing the CPU to handle multiple tasks concurrently in non-secure mode, thus maintaining task handling capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If frequent mode switching occurs between secure and non-secure modes, then secure operations can be performed, but system performance deteriorates

Engineering Contradiction:
Improvesecure operation capabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary action by having the secure module pre-process tokens in non-secure mode before they reach the CPU. This includes initial validation and preparation of token data, so that when the CPU does switch to secure mode, the operation can be completed quickly with minimal overhead. This preliminary processing reduces the frequency and duration of secure mode transitions, thereby improving overall system performance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11748493B2Secure asset management system
Publication Date: 2023.09.05 RAMBUS INC
  • US11748493B2 patent drawing
  • US11748493B2 patent drawing

AI summary

A system can include a processor having a secure mode and a non-secure mode, and a secure module configured to respond to tokens posted by the processor in the secure mode. Each token can identify a secure asset, and source and destination addresses within secure and public address spaces. The secure module can include a memory storing secure assets identifiable by the tokens and a memory access circuit to read data from source addresses and write processed data to destination addresses. The system can further include a cryptography engine configured to process the read data using identified secure assets. The secure module can respond to tokens posted in the non-secure mode. The memory can store, with each secure asset, a respective rule defining the address spaces where the memory access circuit may read and write data. The secure module can ignore tokens that do not satisfy respective rules.