Secure Hardware Memory Manager for Multi-Host TLB Isolation
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Solution Overview
Problem
Ensuring data privacy and efficient memory management across multiple hosts in a shared memory environment poses challenges due to vulnerabilities and performance degradation in SoC architecture, particularly in updating memory management units (MMUs) that share common memory.
Innovation Solution
A secure hardware-based memory management unit is implemented for multi-host systems, utilizing a hardware memory manager to synchronize and efficiently allocate, deallocate, and share memory resources, ensuring data privacy and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MMUs of multiple hosts are updated dynamically to share common memory, then memory sharing capability is improved, but data privacy security deteriorates
Solution Approach 1:
A hardware memory manager is introduced as an intermediary component between multiple hosts and the shared memory system. The memory manager includes page table circuitry and a memory management controller that mediates all memory access requests, performing security checks and synchronization operations to ensure data privacy while enabling memory sharing across hosts.
2Reliability
If MMU updates are synchronized across multiple hosts, then data privacy is improved, but system performance deteriorates
Solution Approach 1:
The memory management controller implements self-service mechanisms through automatic synchronization protocols and hardware-based security checks. The system performs self-validation of memory access requests and automatic coordination of MMU updates across hosts, reducing the need for external intervention and minimizing performance overhead.
3Reliability
If hardware-based memory management is implemented, then security against software attacks is improved, but device complexity increases
Solution Approach 1:
The hardware memory management system is segmented into distinct functional modules: page table circuitry for storing memory mapping information, memory management controller for coordinating updates and performing security checks, and interface circuitry for communicating with host processors. This segmentation allows each component to perform its function independently, improving security while managing complexity through modular design.
Data Source
AI summary
Techniques for hardware-based secure memory management. An example apparatus comprises: a NoC interconnect fabric; first interface circuitry to couple host processors to the NoC interconnect fabric; a hardware memory manager coupled to the NoC interconnect fabric, the hardware memory manager comprising: page table circuitry to store page management information in a plurality of page table entries (PTEs), each PTE corresponding to a TLB entry, the page management information including a host identifier (ID) field to indicate a host processor associated with the PTE entry; a memory management controller to perform security checks on commands received from the host processors, wherein responsive to a first command from a first host processor to perform an allocation or deallocation of a first TLB entry, the memory management controller is to prevent the allocation or deallocation if a first host ID if the first PTE does not correspond to the first host processor.