Secure NVRAM Access for Low-Power SoC via Trusted Channel
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Solution Overview
Problem
Portable computing devices face challenges in providing secure and efficient access to non-volatile random access memory (NVRAM) due to power consumption and latency issues associated with encryption and data retention, as well as potential unauthorized access and incomplete power-down operations.
Innovation Solution
A system and method that create a trusted channel to secure NVRAM by determining a power-saving software program to be executed on the SoC, loading a software image to the secure NVRAM, and powering down all other SoC processing devices except the one executing the software, utilizing a pass gate mechanism for authentication and encryption to ensure secure access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption is used to secure NVRAM contents, then security and privacy are improved, but read/write latency increases due to de-encryption/encryption operations
Solution Approach 1:
The patent applies preliminary action by pre-loading the software image containing encryption keys and decryption algorithms into the NVRAM before the low-power state is entered. This ensures that when the system wakes from low-power mode, the decryption operations can immediately proceed without requiring the system to be fully powered up first, thereby reducing the perceived latency while maintaining security through encrypted storage.
2Reliability
If NVRAM is overwritten/erased upon power-down, then security is improved by preventing unauthorized access, but power consumption increases and incomplete operations may occur during bad power-down
Solution Approach 1:
The patent extracts the security-critical data (software image with encryption keys) from the volatile memory and stores it in the non-volatile NVRAM before power-down. This allows the system to maintain security credentials without requiring continuous power to preserve them, eliminating the need to rewrite NVRAM contents on every power-down while still preventing unauthorized access through the encrypted storage mechanism.
3Use of energy by moving object
If all SoC processing devices are powered down to save power, then power efficiency is improved, but system responsiveness decreases due to complete shutdown
Solution Approach 1:
The patent segments the SoC processing devices into different power states: the main processing devices are powered down to save energy, while a dedicated low-power processing device remains active to handle wake-up events and manage the transition out of low-power mode. This segmentation allows the system to maintain minimal responsiveness for power management functions while achieving significant power efficiency gains.
Data Source
AI summary
Systems and methods are disclosed for managing memory access for low-power use cases of a system on chip. One such method comprises booting a system on chip (SoC) comprising a plurality of SoC processing devices. A trusted channel is created to a secure non-volatile random access memory (NVRAM). The method determines a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices. A software image associated with the power-saving software program is loaded to the secure NVRAM. In response to loading the software image to the secure NVRAM, each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM are powered down.