Secure OS CPU Core Allocation via Mask in Multi-Processor Systems

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Solution Overview

Problem

Current multi-processor systems in electronic devices face performance issues due to limited functionality of the secure Operating System (OS), which restricts the allocation of CPU cores, leading to single-core parallelization and inefficient execution of computationally intensive secure applications, and also suffer from power management inefficiencies and security vulnerabilities.

Innovation Solution

A method and apparatus that enable a multi-processor system to operate with both secure and non-secure OSs, where the secure OS assigns CPU cores through a CPU mask, allowing dynamic allocation and enabling/disabling of CPU cores based on computational load, optimizing resource usage and improving performance by enabling multi-threading and secure mode operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the secure OS uses a resource allocated according to a communication process of the rich OS, then the secure OS can operate with limited functionality, but the secure OS cannot obtain necessary CPU cores allocated to secure OS threads and cannot enable idle CPU cores

Engineering Contradiction:
Improvefunctionality of secure OSVSAvoidperformance of secure OS operations
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments CPU core management into two independent parts: the rich OS manages general CPU allocation and idle core enablement, while the secure OS independently manages CPU core assignment to secure threads through the CPU mask mechanism. This segmentation allows each OS to optimize its operations without being constrained by the other's limitations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a CPU mask as an intermediary data structure that communicates CPU core allocation requirements from the secure OS to the rich OS. The CPU mask acts as a mediator that enables the secure OS to indirectly control CPU core assignment while the rich OS handles the actual hardware enablement, resolving the dependency issue.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the secure OS executes threads on assigned CPU cores without enabling them first, then the secure OS can simplify its operation, but the CPU cores remain disabled and cannot execute threads

Engineering Contradiction:
Improveoperation simplicity of secure OSVSAvoidexecution capability of CPU cores
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements preliminary action by having the rich OS enable idle CPU cores before the secure OS assigns them to secure threads. The secure OS sets the CPU mask to indicate which cores need to be enabled, and the rich OS performs the enablement operation in advance, ensuring cores are ready for thread execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent establishes a feedback mechanism where the secure OS notifies the rich OS of its CPU core allocation needs through the CPU mask, and the rich OS responds by enabling the appropriate cores. This feedback loop ensures that CPU cores are enabled precisely when needed, optimizing both operation simplicity and execution capability.

Inventive Principle:
Principle #23Feedback

3Use of energy by moving object

If the mobile OS disables individual CPU cores to reduce power consumption, then power management is improved, but the secure OS cannot access necessary CPU cores for parallel execution

Engineering Contradiction:
Improvepower consumption of electronic deviceVSAvoidparallel execution capability of secure OS
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent implements dynamics by enabling the rich OS to dynamically control the enablement state of CPU cores based on power management requirements and secure OS needs. The rich OS can enable or disable specific cores while the secure OS maintains its thread allocation through the CPU mask, allowing flexible adaptation between power saving modes and performance requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies local quality by enabling specific CPU cores only when needed for secure thread execution, rather than keeping all cores enabled. The rich OS selectively enables cores based on the CPU mask indications from the secure OS, optimizing power consumption while ensuring necessary cores are available for parallel execution.

Inventive Principle:
Principle #3Local quality

4Device complexity

If the secure OS operates without multi-threading support, then the secure OS maintains simplicity and security, but computationally intensive secure applications cannot execute efficiently

Engineering Contradiction:
Improvecomplexity of secure OSVSAvoidexecution speed of secure applications
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent achieves universality by enabling the secure OS to utilize multiple CPU cores for parallel thread execution while maintaining its simplified architecture. The secure OS can assign multiple threads to different cores through the CPU mask mechanism, making it universally applicable to both simple and computationally intensive secure applications without requiring fundamental architectural changes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10740496B2Method and apparatus for operating multi-processor system in electronic device
Publication Date: 2020.08.11 SAMSUNG ELECTRONICS CO LTD
  • US10740496B2 patent drawing
  • US10740496B2 patent drawing
  • US10740496B2 patent drawing

AI summary

A method and an apparatus for operating a multi-processor system of an electronic device. The electronic device includes a memory for storing commands for running a secure Operating System (OS) and a non-secure OS, and at least one processor including a plurality of processor cores. Upon generation of at least one secure OS thread in the secure OS installed on the electronic device, the at least one processor generates and sends information indicating a secure mode operation request by assigning at least one of the processors cores in the secure OS, and executes the secure OS thread on the at least one processor core assigned in a secure mode based on the information.