Secure PLD Debug Configuration for Failure Characterization

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Solution Overview

Problem

Existing programmable logic devices (PLDs) face challenges in securely characterizing and protecting user configurations from subversion, particularly in trusted computing applications, where unauthorized access or manipulation of configuration data can compromise security operations.

Innovation Solution

A secure programmable logic device failure characterization system that enables secure erasure and failure identification without data loss, using encrypted and signed configuration data, along with a security engine and configuration engine to manage and authenticate configurations, ensuring secure operation and protection against unauthorized access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If configuration data is protected and locked in PLD to prevent subversion, then security is improved, but the ability to debug and characterize failures is worsened

Engineering Contradiction:
ImprovesecurityVSAvoidfailure characterization
Core Design Contradiction:
ReliabilityVSEase of repair

Solution Approach 1:

The patent introduces a secure debug mode as an intermediary state that allows failure characterization without compromising configuration security. This mode acts as a mediator between the locked configuration state and the debugging process, enabling technicians to characterize failures while the configuration remains protected and locked in the background.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the PLD operation into distinct modes: a normal locked mode for secure operation and a secure debug mode for failure characterization. This segmentation allows the system to maintain security during normal operation while enabling debugging capabilities when needed, by switching between these segmented operational states.

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If configuration data is encrypted and protected, then unauthorized access is prevented, but diagnostic processing becomes more difficult

Engineering Contradiction:
Improveunauthorized accessVSAvoiddiagnostic processing
Core Design Contradiction:
Object-affected harmful factorsVSDifficulty of detecting and measuring

Solution Approach 1:

The secure debug mode serves as an intermediary mechanism that enables diagnostic processing without requiring decryption or access to the encrypted configuration data. The system can perform diagnostic operations and characterize failures while the configuration remains encrypted and protected, using the intermediary debug mode to bridge the gap between security and diagnostics.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If PLD is locked to customer configuration, then configuration protection is improved, but the device cannot be reprogrammed or upgraded

Engineering Contradiction:
Improveconfiguration protectionVSAvoidreprogrammability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic behavior to the locked PLD by enabling switching between normal operation mode and secure debug mode. The device maintains its locked state for configuration protection but dynamically transitions to debug mode when failure characterization is needed, allowing reprogrammability and upgrading capabilities while preserving configuration protection through this dynamic mode switching mechanism.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3791304B1Failure characterization systems and methods for programmable logic devices
Publication Date: 2026.02.18 LATTICE SEMICON CORP
  • EP3791304B1 patent drawingFigure 1
  • EP3791304B1 patent drawingFigure 2
  • EP3791304B1 patent drawingFigure 3

AI summary

Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.