Secure Processor Instruction Monitoring for APT Detection
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Solution Overview
Problem
Existing malware detection techniques are inadequate for detecting sustained computing attacks like advanced persistent threats (APT) in cloud environments, as they are designed for traditional 'hit and run' attacks and fail to identify long-term infiltration and data extraction.
Innovation Solution
A framework that monitors hardware-level instructions using secure processors, such as ARM Trustzone and AMD secure processors, to detect transitions and collect key performance indicators (KPIs) for identifying APT attacks, employing models to distinguish between legitimate and malicious activities, and migrates workloads to secure instances to prevent further damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional malware detection techniques are used, then detection simplicity is maintained, but detection capability against sustained computing attacks deteriorates
Solution Approach 1:
The patent implements nested monitoring by placing a virtual machine monitor within a guest virtual machine, which in turn monitors secure processor instructions. This nested structure enables the detection system to operate at multiple levels (hardware instruction level, virtual machine level, and workload level), thereby detecting sophisticated APT attacks that would evade traditional single-level detection methods while maintaining a manageable system architecture through hierarchical organization.
Solution Approach 2:
The patent introduces a kernel image as an intermediary component that acts as a bridge between the secure processor and the detection system. The kernel image collects metrics from secure processor instructions and translates them into detectable patterns, enabling the detection system to analyze hardware-level activities without direct access to the processor internals, thus improving detection capability while maintaining system modularity.
2Measurement precision
If hardware-level monitoring is implemented, then detection precision is improved, but measurement difficulty increases
Solution Approach 1:
The patent extracts specific metric collection functionality into a separate kernel image component that runs within the virtual machine environment. This extracted kernel image specifically monitors secure processor instructions and extracts relevant metrics (such as instruction cache transitions and execution patterns) without requiring the entire detection system to directly analyze raw hardware instructions, thereby maintaining high measurement precision while reducing overall system complexity.
Solution Approach 2:
The patent creates a virtual copy of the secure processor's instruction execution environment within the monitored virtual machine. By copying the essential instruction execution patterns and metrics into this virtual environment, the system can analyze instruction behavior without directly intercepting or modifying actual hardware instructions, thus maintaining measurement precision while simplifying the detection process through software-based analysis.
3Reliability
If continuous monitoring is performed, then detection reliability is improved, but energy consumption increases
Solution Approach 1:
The patent implements periodic monitoring by having the kernel image collect metrics at specific intervals rather than continuously analyzing every instruction. The system monitors secure processor instructions periodically, collecting key metrics such as instruction cache transitions and execution patterns at defined time points, which maintains detection reliability for sustained APT attacks while significantly reducing the continuous energy consumption associated with constant analysis.
Solution Approach 2:
The patent applies partial monitoring by focusing only on specific critical metrics from secure processor instructions rather than analyzing all instruction activities. The kernel image selectively collects metrics related to instruction cache transitions and execution patterns that are most indicative of APT attacks, performing partial analysis on relevant data subsets rather than exhaustive monitoring of all processor activities, thereby reducing energy consumption while maintaining detection effectiveness.
Data Source
AI summary
Techniques are described herein for advanced persistent threat detection. An example method can include a device receiving a message identifying an instruction loaded onto an instruction cache of a secure processer. The device can transmit a control instruction to configure a kernel image to collect a metric over a first time interval, the metric being generated based at least in part on the secure processor executing the instruction during the first time interval. The device can receive the first metric from the kernel image, the metric being indicative of a transition of the secure processor from a non-secure state to a secure state. The device can determine whether the secure processor is undergoing a computing attack based on the metric. The device can transmit the determination of whether the secure processor is undergoing a computing attack to a sender of the message.