Secure Processor Data Bus with Red/Black Partitioning
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Solution Overview
Problem
Existing FPGA designs face challenges in maintaining secure separation of red (unencrypted) and black (encrypted) data when communication is required between physically separate partitions, particularly on a common data bus, which can lead to data exposure and violation of red/black separation.
Innovation Solution
A circuit with three partitions and state control registers allows a single processor to communicate with both red and black peripherals by switching between operational modes, ensuring secure data separation through controlled access via data gates and a bus bridge, preventing data leaks even in case of failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common data bus is used for communication between processor and peripherals in different SCC partitions, then resource utilization is reduced, but red/black data separation cannot be ensured leading to potential data exposure
Solution Approach 1:
The data bus is segmented into separate red and black data paths with dedicated gates controlling access. The single physical bus is divided into multiple logical channels that can be independently controlled to maintain red/black separation while sharing the same physical infrastructure.
Solution Approach 2:
The data bus configuration is made dynamic through state control registers that can switch between different operational modes (red mode, black mode, mixed mode). This allows the system to adaptively change the bus configuration based on the current operational requirements while maintaining security.
2Reliability
If multiple processors are used in separate FPGAs or SCC partitions to process red and black data separately, then red/black data separation is ensured, but resource utilization and system complexity increase
Solution Approach 1:
A single processor is designed to perform multiple functions by operating in different modes (red mode and black mode). The processor can securely handle both red and black data through mode switching controlled by state control registers, eliminating the need for separate processors while maintaining security.
Solution Approach 2:
State control registers act as intermediaries between the processor and the data bus, controlling which data path (red or black) is active at any given time. This mediation mechanism enables a single processor to securely interact with both red and black peripherals without direct exposure between the data types.
3Reliability
If different data buses are used for instructions and data, then data security can be improved, but resource utilization increases and bus availability decreases
Solution Approach 1:
The data bus is segmented into red and black channels that can be independently controlled. This segmentation allows secure separation of data types while maintaining a single physical bus infrastructure, avoiding the need for multiple separate buses for instructions and data.
Data Source
AI summary
System and method for implementing a secure processor data bus are described. One embodiment is a circuit comprising a processor disposed in a processor partition, the circuit further comprising a first set of peripherals disposed in a first peripheral partition; a second set of peripherals disposed in a second peripheral partition physically isolated from the first peripheral partition; a first state control register for controlling access to the first set of peripherals by the processor; and a second state control register for controlling access to the second set of peripherals by the processor. When the first and second state control registers are in a first mode of operation, the processor has read and write access to the first set of peripherals and write only access to the second set of peripherals. When the first and second state control registers are in a second mode of operation, the processor has read and write access to the second set of peripherals and read only access to the first set of peripherals.