Secure Processor Authentication with OTP Power-Off Detection
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Solution Overview
Problem
Existing electronic devices are vulnerable to unauthorized access through brute-force user authentication attempts, and sudden power-off events can erase authentication records, increasing the risk of unauthorized access.
Innovation Solution
A secure processor with a volatile memory to store failure counts and a one-time programmable (OTP) memory to store event counts, which updates and compares these counts upon power-on to detect sudden power-off events and enforce authentication throttling based on pre-event failure counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If authentication records are stored in volatile memory, then authentication failure counts can be tracked and throttling can be enforced, but the records are lost when power is turned off suddenly
Solution Approach 1:
The patent applies preliminary action by storing the event count (which reflects authentication failure state) in OTP memory before a sudden power-off can occur. The OTP memory retains this count information permanently, so when the device restarts, the authentication state can be recovered without loss, preventing unauthorized access through brute-force attempts.
2Reliability
If OTP memory is used to store event count, then authentication records are preserved across power cycles, but memory resources are consumed
Solution Approach 1:
The patent extracts only the essential authentication state information (event count reflecting failure threshold) and stores it in OTP memory, rather than storing complete authentication records. This selective extraction preserves the necessary security state while minimizing memory resource consumption.
Solution Approach 2:
The patent applies local quality by using different memory types for different purposes: volatile memory for temporary authentication state during active operation, and OTP memory for permanent preservation of the event count. This localized use of memory properties optimizes both reliability and resource efficiency.
3Reliability
If authentication throttling is enforced, then brute-force attempts are prevented, but user authentication is restricted during throttle period
Solution Approach 1:
The patent implements periodic action through authentication throttling, where after a certain number of failed attempts (reaching the event count threshold), authentication is temporarily restricted for a throttle period. This periodic restriction prevents continuous brute-force attempts while eventually allowing legitimate users to authenticate again.
Solution Approach 2:
The patent applies preliminary anti-action by proactively restricting authentication before a brute-force attack can succeed. When the event count reaches the threshold, the system preemptively blocks further authentication attempts during the throttle period, countering potential attacks before they can compromise security.
Data Source
AI summary
Electronic device including SoC which includes secure processor performing user authentication based on authentication data received from user, and nonvolatile memory device storing first event count is disclosed. The secure processor includes volatile memory that stores failure count increasing as the user authentication fails and being reset as the user authentication succeeds, security module that restricts the user authentication of the user during first time period when the failure count reaches first threshold value, and OTP memory that stores second event count increasing as throttle level corresponding to the failure count changes. When the user authentication succeeds and when power-off request for the system on chip is generated, the first event count is updated based on the second event count. When the secure processor is powered on after the SoC is powered on, the security module compares the first and second event count to determine whether sudden power-off occurs.