Secure Processor Obfuscating Execution Patterns
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Solution Overview
Problem
Existing secure computation methods, such as FHE, ORAMs, and TPMs, are incomplete or impractical due to performance penalties, limited functionality, and inability to hide processor activity and memory access patterns, making them unsuitable for general-purpose processing.
Innovation Solution
A secure processor architecture that obfuscates program execution and memory access patterns by uniformly exercising computational and memory interface circuits, regardless of operational requirements, to present uniform power consumption and memory access patterns, thereby preventing information leakage to observers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fully homomorphic encryption is used for secure computation, then security is improved, but processing speed deteriorates significantly
Solution Approach 1:
The processor is divided into multiple execution units (EU0-EU7) that can operate in different modes (obfuscated execution, clear execution, homomorphic execution). This segmentation allows the system to use FHE only when necessary while maintaining high-speed clear execution for other tasks, thus resolving the contradiction between security and processing speed.
Solution Approach 2:
The processor dynamically switches between different execution modes based on security requirements. The mode selection logic determines whether to use obfuscated execution mode (for security), clear execution mode (for speed), or homomorphic execution mode (for specific secure workloads), allowing the system to optimize performance while maintaining security when needed.
2Reliability
If obfuscated execution mode is used to hide processor activity, then security is improved, but processing speed deteriorates
Solution Approach 1:
Different parts of the processor can operate in different execution modes simultaneously. The obfuscated execution mode is applied locally to specific execution units when security is needed, while other units continue to operate in high-speed clear mode, thus maintaining overall system performance while providing security where required.
Solution Approach 2:
The processor dynamically switches between obfuscated and clear execution modes based on the security requirements of the current workload. This dynamic mode switching allows the system to maintain high processing speed for non-sensitive operations while providing strong security guarantees for sensitive computations.
3Reliability
If memory interface circuits are exercised uniformly to obfuscate access patterns, then security is improved, but energy consumption increases
Solution Approach 1:
The memory interface circuits are exercised periodically at fixed time intervals regardless of actual memory access needs. This periodic exercise creates uniform access patterns that obfuscate real memory access behavior, preventing side-channel attacks while using energy at predictable periodic intervals rather than continuously.
Data Source
AI summary
A technique for secure computation obfuscates program execution such that observers cannot detect what instructions are being run at any given time. Rather, program execution and memory access patterns are made to appear uniform. A processor operates based on encrypted inputs and produces encrypted outputs. In various examples, obfuscation is achieved by exercising computational circuits in a similar way for a wide range of instructions, such that all such instructions, regardless of their operational differences, affect the processor's power dissipation and processing time substantially uniformly. Obfuscation is further achieved by limiting memory accesses to predetermined time intervals, with memory interface circuits exercised regardless of whether a running program requires a memory access or not. The resulting processor thus reduces leakage of any meaningful information relating to the program or its inputs, which could otherwise be detectable to observers.


