Secure Processor Vector Table Register Lock Controller
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Solution Overview
Problem
The reliability of firmware or ROM code during the boot-up process of storage devices is compromised due to the lack of secure mechanisms to prevent external manipulation and ensure integrity verification.
Innovation Solution
A secure processor with a vector table register and a lock controller is implemented, which stores boot-up address information and manages lock counts to securely lock and unlock this information, preventing external tampering and ensuring the integrity of the boot-up process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the vector table register is made accessible for updates during boot-up, then the adaptability of the system is improved, but the security and reliability are compromised due to external manipulation risks
Solution Approach 1:
The vector table register transitions from a static locked state to a dynamic unlocked state temporarily during boot-up, allowing controlled updates. The lock controller dynamically manages the register's accessibility based on operational phase, enabling updates only when needed while maintaining security otherwise.
Solution Approach 2:
The lock controller preemptively locks the vector table register before the boot-up process begins, preventing any external manipulation. The register is unlocked only at the specific moment when firmware updates are legitimately required, and re-locked immediately after, ensuring security through advance protective action.
2Reliability
If the vector table register is locked to prevent manipulation, then the security is improved, but the ability to update boot-up address information is reduced
Solution Approach 1:
The locking mechanism is not static but dynamically controlled. The lock controller temporarily releases the lock during the boot-up phase when updates are legitimate, then re-establishes it afterward. This dynamic behavior maintains security while enabling necessary updates.
Solution Approach 2:
The lock controller applies a preliminary protective lock to prevent manipulation, but includes a predetermined exception mechanism that temporarily suspends this protection during authorized boot-up operations. This preliminary anti-action is designed with built-in flexibility for legitimate updates.
3Reliability
If a lock controller is implemented to manage the vector table register, then the security mechanism is improved, but the device complexity increases
Solution Approach 1:
The lock controller is integrated within the existing processor architecture rather than being a completely separate component. It communicates with the vector table register through established control interfaces, merging security functionality into the existing structural framework to minimize added complexity.
Solution Approach 2:
The lock controller serves multiple functions: it manages the vector table register locking, counts update operations, and coordinates with the secure core. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in overall device complexity.
Data Source
AI summary
Provided are a secure processor, an operating method thereof, and a storage device including the secure processor. Provided is a secure processor including a secure core including a vector table register containing boot-up address information, and a vector table register controller configured to communicate with the secure core, wherein the vector table register controller includes a lock controller configured to lock the vector table register and a count register configured to store a lock count value that is the number of times the boot-up address information of the vector table register is updated.