Multiple Secure Virtual Processors with Per-VP SEPT Isolation
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Solution Overview
Problem
Existing computing systems lack the ability to execute software shielded from a trust domain (TD) while retaining access to the TD's memory, state, and metadata, particularly in the context of virtual trusted platform module (vTPM) platform configuration registers (PCRs), where attestation keys (AIKs) need protection from compromise.
Innovation Solution
Implement multiple secure extended page tables (SEPTs) for each trust domain, allowing each virtual processor (VP) to have a unique view of TD memory, enabling secure data exchange and communication through shared private memory without the need for networking and encryption, and enhance security with per-VP SEPT access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single secure extended page table (SEPT) is used for all virtual processors in a trust domain, then memory access is simplified, but security is compromised because all VPs can access the same memory views and a compromised TD could access attestation keys
Solution Approach 1:
The patent divides the single SEPT into multiple per-VP SEPTs, where each virtual processor has its own dedicated secure extended page table. This segmentation isolates memory access permissions so that each VP can only access its designated memory regions, preventing compromised VPs from accessing other VPs' memory or attestation keys stored in the vTPM
Solution Approach 2:
Each VP is assigned specific memory regions with unique access permissions through its own SEPT. The vTPM's attestation keys are stored in a dedicated memory region that is locally accessible only to authorized VPs, while other memory regions are accessible to different subsets of VPs. This local quality control ensures that each VP has appropriate access rights without exposing the entire memory space
2Reliability
If multiple per-VP secure extended page tables (SEPTs) are implemented, then security is improved by isolating memory access, but device complexity increases
Solution Approach 1:
The VMM (Virtual Machine Monitor) acts as an intermediary that manages the creation, maintenance, and switching of multiple per-VP SEPTs. The VMM handles the complexity of coordinating memory access across multiple VPs and vTPMs, translating high-level memory management requests into specific SEPT operations. This intermediary approach shields the system from the inherent complexity while maintaining security benefits
Solution Approach 2:
The VMM is designed to universally manage multiple SEPTs across multiple VPs and vTPMs using a standardized interface. The same VMM infrastructure handles SEPT creation, switching, and validation for all VPs, reducing the operational complexity despite the increased number of SEPT structures. The multi-functional VMM handles both security enforcement and memory management tasks
3Reliability
If networking and encryption are used for secure data exchange between VPs, then security is maintained, but performance is reduced due to additional processing overhead
Solution Approach 1:
The patent extracts the security enforcement mechanism from the data exchange path by using hardware-enforced SEPTs that automatically prevent unauthorized memory access. Instead of adding encryption layers to every data exchange operation, the security check is extracted into the memory access itself through SEPT validation, allowing legitimate data exchanges to proceed without additional encryption/decryption overhead while still maintaining security
Data Source
AI summary
Providing multiple virtual processors (VPs) for a trusted domain (TD) includes creating a virtual processor control structure (VPCS) for one or more of a plurality of VPs of the TD of a processor in a computing system, the TD including a trust domain control structure (TDCS), the plurality of VPs having views into addresses of private memory of the TD, the VPCS for a VP including a secure extended page table (SEPT) for the VP; and for the VP, initializing the VPCS for the VP by copying selected entries of the TDCS to the SEPT of the VPCS, pointing a SEPT pointer to the VPCS, and setting an entry point for starting execution of the VP by the processor.