Secure Protection Block for SoC Voltage Attack Resistance
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Solution Overview
Problem
Conventional architectures are vulnerable to malicious attacks that manipulate fuse values in one-time programmable fuse arrays, particularly through over-voltage and under-voltage attacks, which can compromise the security of function blocks and fuse arrays in System-on-a-Chip (SoC) devices.
Innovation Solution
The implementation of a secure system design with protection blocks, attack monitoring blocks, and communication networks that incorporate over-voltage and under-voltage tolerant transistors, such as thick-gate-oxide and stacked-transistor configurations, to prevent unauthorized access and ensure secure operation by entering a safe mode in response to abnormal voltage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional voltage supply architecture is used, then ease of operation is improved, but security against voltage manipulation attacks deteriorates
Solution Approach 1:
The system segments the voltage supply architecture by introducing separate protection blocks for each function block. Each protection block independently monitors voltage conditions and controls power delivery to its associated function block, preventing system-wide vulnerability to voltage manipulation attacks while maintaining operational simplicity.
Solution Approach 2:
Protection blocks serve as intermediary components between the voltage supply and function blocks. These intermediaries monitor voltage conditions and intervene to prevent malicious voltage manipulation from reaching sensitive function blocks, thereby enhancing security without complicating the overall operation.
2Reliability
If thick-gate-oxide transistors are used in protection blocks, then resistance to over-voltage attacks is improved, but manufacturing complexity increases
Solution Approach 1:
Thick-gate-oxide transistors are selectively implemented only in protection blocks where over-voltage resistance is critical, rather than throughout the entire system. This localized approach provides the necessary security hardening while minimizing the impact on manufacturing processes and complexity.
Solution Approach 2:
The system employs a composite transistor architecture combining standard transistors in function blocks with thick-gate-oxide transistors in protection blocks. This composite approach allows each component to use the most appropriate technology for its specific function, balancing security requirements with manufacturing feasibility.
3Difficulty of detecting and measuring
If attack monitoring blocks are added, then detection capability is improved, but device complexity increases
Solution Approach 1:
Attack monitoring functionality is merged with the existing protection blocks rather than being implemented as separate standalone components. The protection blocks simultaneously perform voltage monitoring, attack detection, and power control functions, thereby enhancing detection capability while avoiding additional complexity from redundant structures.
Solution Approach 2:
The protection blocks are designed as multi-functional units that simultaneously provide voltage monitoring, attack detection, and power control. This universal design approach allows a single component to perform multiple security functions, reducing overall system complexity while maintaining comprehensive attack detection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly enhances the resistance of SoC devices to multi-phase attacks, ensuring the confidentiality of fuse values and security keys by ensuring protection blocks fail before function blocks, thereby maintaining system security and integrity.
Implementation Method 1
the first transistor has a first gate oxide breakdown voltage that is greater than a second gate oxide breakdown voltage of the second transistor
Data Source
AI summary
An embodiment includes an apparatus comprising: power supply pins to couple to a power supply; a protection block, including a first transistor, to: (a) determine whether voltage from the power supply pins meets a predetermined condition, and (b) in response to determining whether the predetermined condition is met, communicate a first communication to at least one of first and second function blocks; and the first function block, coupled to the protection block and the power supply pins, including a second transistor and at least one fuse that corresponds to a security key; wherein the first transistor is at least one of: (a) connected in series with at least one other transistor, and (b) having a first gate oxide breakdown voltage that is greater than a second gate oxide breakdown voltage of the second transistor. Other embodiments are described herein.