Secure RTC Clock-Line Frequency Scaling for Low Power
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Solution Overview
Problem
Current secure real-time clock systems in portable electronic devices face high power consumption issues due to the continuous operation of the clock line at 32.768 kHz frequency, especially when powered by an auxiliary source, which depletes the power source quickly.
Innovation Solution
A secure real-time clock system that dynamically adjusts the frequency of the clock line signal from 32.768 kHz to a reduced frequency, such as 1.024 kHz, using a frequency divider, allowing the system to operate in low power mode while maintaining accuracy, thereby reducing power consumption from 2.5 μA to approximately 80 nA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock line operates continuously at 32.768 kHz frequency to maintain accurate RTC tracking, then the accuracy of date and time tracking is improved, but the power consumption increases to approximately 2.5 μA, which is 50% of the desired power budget
Solution Approach 1:
The system dynamically adjusts the clock line frequency based on power mode. In low power mode, the frequency is reduced from 32.768 kHz to 1.024 kHz (by dividing by 32), while in accurate time mode, the full frequency is restored. This dynamic frequency adjustment resolves the contradiction by adapting the clock line operation to current power availability, reducing consumption when auxiliary power is used while maintaining accuracy when full power is available.
Solution Approach 2:
The patent changes the frequency parameter of the clock line signal based on power mode. By implementing a frequency divider that divides the oscillator frequency by 32 in low power mode, the clock line frequency parameter is changed from 32.768 kHz to 1.024 kHz. This parameter change directly addresses the contradiction by reducing power consumption through frequency reduction while providing a mechanism to restore full frequency when accuracy is prioritized.
2Reliability
If the RTC is implemented in the microprocessor with oscillator in PMIC to provide greater security and additional security features, then the security of the RTC is improved, but the power consumption of the system increases due to the required clock line connection
Solution Approach 1:
The system implements dynamic frequency scaling of the clock line based on power mode detection. When auxiliary power is detected (low power mode), the clock line frequency is reduced to 1.024 kHz, significantly reducing power consumption. When main power is available (accurate time mode), the full 32.768 kHz frequency is restored. This dynamic adjustment resolves the contradiction by allowing the secure RTC implementation while adapting clock line power consumption to current operational requirements.
Solution Approach 2:
The system periodically monitors power mode conditions and adjusts clock line frequency accordingly. The power mode detection mechanism continuously assesses power availability and switches between frequency modes, creating a periodic adaptation cycle that balances security requirements with power consumption constraints based on current operational context.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively reduces power consumption by 50% in low power mode without compromising the accuracy of the real-time clock, aligning with the desired power budget of 5 μA or less, making it suitable for next-generation portable devices.
Implementation Method 1
A secure real-time clock system that dynamically adjusts the frequency of the clock line signal from 32.768 kHz to a reduced frequency, such as 1.024 kHz, using a frequency divider
Data Source
AI summary
A secure real time clock (RTC) system is provided, comprising a secure RTC, a frequency signal generator, and a frequency adjuster connected between the secure RTC and the frequency signal generator to receive a signal having a first frequency from the frequency signal generator. On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC, and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC. A clock line transmits the signal having the first frequency and the signal having the second frequency from the frequency adjuster to the secure RTC, and has a first power consumption when transmitting the signal having the first frequency and a second power consumption when transmitting the signal having the second frequency, the first power consumption being greater than the second power consumption.