Secure Scan Entry Flip-Flop Reset Circuit
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Solution Overview
Problem
The integration of a secure domain in semiconductor devices complicates scan testing, as it poses a risk of extracting confidential information when the device is placed in scan mode, making it impractical to exclude the secure domain from testing due to increasing functionality.
Innovation Solution
An integrated circuit design that utilizes circuitry to select scan modes and generates a reset for the secure domain's flip-flops between the assertion of the SCAN_TEST_EN and SCAN_TST_UPD signals, ensuring that confidential information cannot be extracted during testing by maintaining the secure domain in a reset state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the secure domain is excluded from scan chains to prevent extraction of confidential information, then security is improved, but testing completeness deteriorates
Solution Approach 1:
The patent applies preliminary action by resetting the secure domain flip-flops to a known state before entering scan mode. The reset signal is generated in advance based on the detection of scan mode entry (through specific signal sequences), ensuring that confidential information is cleared before any scan operations can extract data, thus maintaining security while allowing complete testing
2Productivity
If scan mode is entered to perform comprehensive testing, then testing completeness is improved, but security deteriorates due to potential extraction of confidential information
Solution Approach 1:
The patent applies preliminary anti-action by implementing a mechanism that detects scan mode entry through specific signal sequences (TAP_DPISR, TAP_DRS1, TAP_DRS2) and automatically generates a reset signal to clear the secure domain before testing begins. This preemptive measure counteracts the security risk by ensuring confidential information is erased before any scan operations can potentially extract it
3Productivity
If the secure domain is included in scan chains for comprehensive testing, then testing completeness is improved, but the complexity of the test system increases
Solution Approach 1:
The patent applies universality by implementing a multi-functional signal sequence mechanism that serves both as the scan mode entry protocol and as the trigger for secure domain reset. The same TAP controller signals (TAP_DPISR, TAP_DRS1, TAP_DRS2) that indicate scan mode entry also automatically trigger the reset generation, eliminating the need for separate control logic and reducing test system complexity
Data Source
AI summary
An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.