Secure System-on-Chip with Input Encryption Module

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Solution Overview

Problem

Existing system-on-chip technologies lack a robust and dynamic encryption mechanism to ensure secure data processing and storage, with data often being exposed in clear form during processing, which compromises security, especially in multi-processing architectures.

Innovation Solution

A secure system-on-chip design that incorporates an input encryption module and an output decryption module, along with an encryption/decryption engine, to maintain an internal encryption layer for all data, ensuring that data are encrypted upon entry, processed in a secure state, and re-encrypted before exit, using a unique key for secure processing and storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data are decrypted and stored in clear form during processing, then processing speed and accessibility are improved, but security is compromised due to exposure of clear data

Engineering Contradiction:
Improveprocessing speedVSAvoidsecurity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system applies encryption to data before they are stored in memory, and maintains them in encrypted state during storage. The decryption only occurs temporarily during active processing by the CPU, and re-encryption is performed immediately after processing. This preliminary and continuous encryption approach ensures data are protected at rest while still allowing efficient processing when needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an encryption/decryption engine as an intermediary component between the CPU and memory systems. This engine manages the encryption/decryption operations and controls when data are decrypted for processing, acting as a mediator that balances security requirements with processing needs. The engine ensures that clear data exist only temporarily in the CPU register during active processing, not in memory or I/O buffers.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If an encryption layer is added to all data entering and exiting the system-on-chip, then security is improved, but device complexity increases

Engineering Contradiction:
ImprovesecurityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The encryption/decryption engine is designed as a universal component that handles encryption and decryption operations for all data paths within the system-on-chip. Rather than implementing separate encryption mechanisms for different data paths (CPU memory, I/O channels, inter-process communication), a single multi-functional engine serves all encryption needs, reducing overall system complexity while maintaining comprehensive security.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If data are continuously encrypted during storage and transmission, then security is improved, but processing overhead increases

Engineering Contradiction:
ImprovesecurityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system implements periodic encryption/decryption cycles rather than continuous encryption throughout the entire data lifecycle. Data are encrypted when stored in memory, decrypted only when actively needed by the CPU for processing, and re-encrypted immediately after processing completes. This periodic approach minimizes the time data spend in decrypted state, reducing security risks while avoiding unnecessary encryption/decryption operations that would degrade performance.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8656191B2Secure system-on-chip
Publication Date: 2014.02.18 NAGRAVISION SA
  • US8656191B2 patent drawing
  • US8656191B2 patent drawing
  • US8656191B2 patent drawing

AI summary

A secure system-on-chip for processing data, the system-on-chip comprising at least a central processing unit (CPU), an input and an output channel, an encryption/decryption engine and a memory, wherein, said input channel comprises an input encryption module to encrypt all incoming data, said output channel comprising an output decryption module to decrypt all outgoing data, said CPU receiving the encrypted data from the input encryption module and storing them in the memory, and while processing the stored data, said CPU reading the stored data from the memory, requesting decryption of same in the encryption/decryption engine, processing the data and requesting encryption of the result by the encryption/decryption engine and storing the encrypted result, outputting the result to the output decryption module for decryption purpose and exiting the decrypted result via the output channel.