Secure Processing Subsystem Anti-Replay Transaction Mechanism

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Solution Overview

Problem

Existing systems with secure processing sub-systems face challenges in preventing rollback or playback attacks, particularly due to limited internal memory and the need for a robust and secure internal power source, which increases costs and space requirements.

Innovation Solution

A transaction-based mechanism is implemented, where during each power cycle, the secure processing sub-system writes start and end transaction data to the internal non-volatile memory, and at the beginning of each power cycle, it checks for pending transactions to prevent data usage from external non-volatile memory if a transaction is still pending.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a secure internal power source is added to the secure processing sub-system to prevent rollback attacks during power interruptions, then security against replay attacks is improved, but device complexity and cost increase

Engineering Contradiction:
Improvesecurity against replay attacksVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the power source dependency from the secure processing sub-system by storing the anti-replay counter in external non-volatile memory instead of requiring an internal power source. The secure element performs cryptographic operations on the counter value without needing to maintain power during transitions, thereby eliminating the need for complex internal power management while preserving security.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary mechanism where the anti-replay counter is stored in external non-volatile memory and processed through cryptographic operations by the secure element. This intermediary approach allows the system to verify data freshness without directly maintaining power to the counter storage, reducing internal complexity while maintaining security.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If internal non-volatile memory is used to store the anti-replay counter, then security against rollback attacks is improved, but the amount of internal memory required increases

Engineering Contradiction:
Improvesecurity against rollback attacksVSAvoidinternal memory
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the anti-replay counter storage from the secure processing sub-system's internal memory to external non-volatile memory. This extraction allows the secure element to maintain security functionality while utilizing minimal internal memory resources, as the counter value is stored externally and processed cryptographically without requiring large internal storage capacity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If the anti-replay counter is stored in volatile memory, then device complexity is reduced, but security against power loss attacks deteriorates

Engineering Contradiction:
Improvedevice complexityVSAvoidsecurity against power loss attacks
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary cryptographic verification process where the anti-replay counter stored in external non-volatile memory is processed through secure cryptographic operations. This intermediary mechanism ensures that even though the counter is stored externally, its integrity and authenticity are verified through cryptographic means, providing security against power loss attacks while maintaining simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the state parameter of the anti-replay counter from volatile to non-volatile storage, ensuring persistence across power cycles. This parameter change maintains security against power loss attacks while the external storage location keeps device complexity low.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250190630A1Method to prevent Anti-replay attack
Publication Date: 2025.06.12 NAGRAVISION SRL
  • US20250190630A1 patent drawing
  • US20250190630A1 patent drawing
  • US20250190630A1 patent drawing

AI summary

A method performed by a system including a secure processing sub-system having an internal non-volatile memory, and a non-volatile memory that is external to the secure processing sub-system. During each power cycle where data stored in the external non-volatile memory is updated, the secure processing sub-system executes a transaction by writing a first transaction data marking the start of the transaction in the internal non-volatile memory upon a first update of the data within the power cycle, and at the end of the power cycle, in case the power cycle ends normally, writing a second transaction data marking the end of the transaction to the internal non-volatile memory. At the beginning of any power cycle, the secure processing sub-system checks if a transaction is still pending in the internal non-volatile memory, and if a transaction is still pending, prevents to use the data stored in the external non-volatile memory.