Secure Virtualized Telemetry for GPU Workload Integrity

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Solution Overview

Problem

Current graphics processing units (GPUs) face challenges in efficiently processing graphics data due to the limitations of fixed function computational units and the need for improved parallel processing techniques, particularly in SIMT architectures, which can lead to inefficiencies in executing program instructions synchronously.

Innovation Solution

Implementing a graphics processing unit with a parallel processing unit that includes a scheduler for efficient workload distribution across processing clusters, utilizing SIMT architectures and secure virtualized telemetry for workload integrity and passive noise analysis, enhancing processing efficiency and security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If fixed function computational units are used in GPUs, then hardware implementation is simpler, but processing versatility and adaptability are limited

Engineering Contradiction:
Improvehardware implementation simplicityVSAvoidprocessing versatility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent implements a hybrid architecture where computational units can dynamically switch between fixed-function modes (for rasterization, texture mapping) and programmable modes (for compute shaders, ray tracing). This allows the same hardware to adapt its functionality based on workload requirements, resolving the contradiction between manufacturing simplicity and processing versatility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The GPU architecture employs universal computational units that can perform multiple functions through configuration rather than dedicated hardware for each function. The same processing cores handle both traditional graphics operations and general-purpose computing tasks, eliminating the need for separate fixed-function units while maintaining hardware efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If SIMT architecture is used to maximize parallel processing, then processing throughput increases, but synchronization overhead and instruction execution efficiency deteriorate

Engineering Contradiction:
Improveprocessing throughputVSAvoidsynchronization overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the SIMT thread execution into independent wavefronts that can be processed separately. Each wavefront contains a subset of threads that execute synchronously, allowing the GPU to manage synchronization at a finer granularity. This segmentation reduces the synchronization overhead compared to synchronizing all threads globally, while still maintaining high parallel throughput through multiple concurrent wavefronts.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The GPU employs periodic scheduling of thread blocks across processing units, where threads are executed in periodic waves rather than continuous synchronous execution. This periodic action allows idle processing units to be utilized by subsequent thread blocks, reducing overall synchronization wait time while maintaining high aggregate throughput through continuous periodic processing cycles.

Inventive Principle:
Principle #19Periodic action

3Reliability

If telemetry data is collected for workload integrity verification, then security and verification capability improve, but system complexity and computational overhead increase

Engineering Contradiction:
Improveworkload integrity verificationVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a dedicated telemetry collection module that acts as an intermediary between the GPU execution units and the verification system. This module captures execution metadata (thread IDs, instruction counts, register states) without interfering with the core processing logic. By isolating telemetry collection in a separate intermediary component, the system achieves reliable workload verification while minimizing complexity in the main processing path.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of modifying the original execution state for verification purposes, the system creates copies of relevant execution metadata (thread states, instruction streams, memory access patterns) for integrity checking. These copies are generated by the telemetry module and used for verification without affecting the primary computation, thus maintaining system reliability while avoiding the complexity of state modification and restoration.

Inventive Principle:
Principle #26Copying

4Measurement precision

If noise analysis is performed on telemetry data, then signal quality and verification accuracy improve, but processing time and computational resources increase

Engineering Contradiction:
Improveverification accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements preliminary noise filtering and characterization during the telemetry data collection phase. Instead of performing complex noise analysis on raw data after collection, the system pre-processes the telemetry stream to identify and filter obvious noise patterns, and pre-characterizes the noise properties (variance, frequency content) for later verification. This preliminary action reduces the computational burden and processing time required for subsequent verification while maintaining high measurement precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250284785A1Workload integrity and passive noise analysis via secure virtualized telemetry
Publication Date: 2025.09.11 INTEL CORP
  • US20250284785A1 patent drawing
  • US20250284785A1 patent drawing
  • US20250284785A1 patent drawing

AI summary

An apparatus providing workload integrity and passive noise analysis via secure virtualized telemetry is disclosed. The apparatus includes processor circuitry comprising a secure telemetry endpoint circuitry to: maintain a fingerprint counter that is to provide measurements over a set of base telemetry counters of the processor circuitry, wherein the base telemetry counters provide measurement data to the secure telemetry endpoint circuitry; receive new measurements from the set of base telemetry counters; apply post-processing to the new measurements to at least one of normalize the new measurements, reduce dimensionality among the new measurements, or reduce attestation false positives to generate a post-processed version of the new measurements; update a value of the fingerprint counter by concatenating the post-processed version of the new measurements to the value; and recompute a hash digest of the fingerprint counter based on the updated value of the fingerprint counter.