Secure Configurable Test Interface for SOC IP Blocks
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Solution Overview
Problem
Traditional electronic design automation (EDA) tools do not fully support the insertion of built-in self-test (BIST) functionality into intellectual property (IP) blocks, especially when IP blocks have distributed functions across multiple layers and third-party components, and require exposing the IP block to the SOC integration team, which is not desirable for security and privacy reasons.
Innovation Solution
A secure and configurable test interface is implemented using SystemVerilog interfaces, mod ports, and interposer circuitry to insert BIST functionality into IP blocks without modifying the register transfer language (RTL) design files, allowing encrypted RTL delivery and reducing complexity in handling design and manufacturing changes across different process nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional EDA tools are used to insert BIST functionality by reading and editing RTL design files, then BIST insertion can be achieved, but the IP block must be exposed to the SOC integration team which compromises security and privacy
Solution Approach 1:
The patent introduces an intermediary interface layer between the IP block and the SOC integration team. This interface allows BIST functionality to be inserted and configured without exposing the internal RTL design files. The intermediary mechanism enables test logic insertion while maintaining encryption and security of the IP block design, resolving the contradiction between ease of manufacture and security protection.
2Device complexity
If flat insertion process is used to insert BIST functionality, then the process can be simplified, but it requires exposing the IP block to the SOC integration team and does not work with nested VHDL blocks
Solution Approach 1:
The patent segments the BIST insertion process into distinct modular components that can operate independently. Instead of requiring a flat insertion process that modifies RTL files directly, the solution divides the functionality into separate interface layers and test logic modules. This segmentation enables compatibility with nested VHDL blocks and encrypted RTL designs while maintaining a manageable complexity level.
3Reliability
If EDA tools modify RTL design files to insert BIST functionality, then test logic can be integrated, but bugs may be introduced and the process lacks scalability across different process nodes
Solution Approach 1:
The patent implements preliminary action by pre-configuring the BIST functionality through a standardized interface before integration into the SOC. Instead of modifying RTL files during the integration process, the test logic is prepared in advance with predefined interface contracts. This preliminary configuration reduces the risk of introducing bugs during modification and enhances scalability across different process nodes by maintaining consistent interface definitions.
Data Source
AI summary
A design for test (DFT) block of a system on a chip (SOC) includes a function mapping interface coupled to a set of function interfaces of an intellectual property (IP) block core; and a core coupled to the function mapping interface by a plurality of test interfaces, the core including an interposer to manage assignments of the plurality of test interfaces from the function mapping interface to a plurality of placeholder interfaces of a collar, wherein the function mapping interface maps the set of function interfaces to the plurality of test interfaces.