Secure Timer Synchronization via Shared Register Space
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Solution Overview
Problem
Existing computing systems face security risks and synchronization challenges due to the need for external ICs to access memory registers, leading to potential unauthorized access and jitter-induced unsynchronization, especially in systems implementing Discontinuous Reception (DRX) for power conservation.
Innovation Solution
Implementing a shared register space that isolates the global counter configuration of a function block from external access, allowing secure timer synchronization through a shared register space that prevents unauthorized access and corrects jitter by resynchronizing timers during boot and mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external ICs access memory registers for timer synchronization, then timer synchronization between function blocks is achieved, but security risks increase due to potential unauthorized access to intellectual property
Solution Approach 1:
The patent divides the register access architecture into segmented levels: shared register space for synchronization data and protected register space for intellectual property. The external IC can access only the shared register space through controlled interfaces, while the protected register space remains inaccessible without proper authorization. This segmentation allows timer synchronization to proceed while isolating sensitive intellectual property from potential unauthorized access.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a controlled register interface that mediates between the external IC and the function block's register space. This intermediary validates and filters access requests, allowing only permitted synchronization operations while blocking unauthorized access attempts. The intermediary layer thus enables necessary communication while maintaining security boundaries.
2Loss of energy
If devices are repeatedly power cycled for DRX operations, then power consumption is reduced, but security risks increase and timer synchronization becomes more difficult due to jitter
Solution Approach 1:
The patent implements preliminary timer value loading into preload registers before power cycling occurs. When the function block wakes from DRX sleep mode, the pre-loaded timer values are already prepared and can be quickly transferred to the global counter with a simple strobe signal, eliminating the need for lengthy resynchronization procedures. This preliminary preparation reduces both the time and complexity of post-wakeup synchronization while maintaining power efficiency.
Solution Approach 2:
The patent enables the function block to autonomously handle timer resynchronization after power cycling by using the shared register space to automatically receive and load timer values from the external IC when needed. The system self-corrects synchronization drift caused by DRX operations without requiring complex external intervention, thereby maintaining reliable timing despite repeated power states.
3Productivity
If global counters are used for timer synchronization, then timing functions are implemented, but jitter causes unsynchronization between devices over time
Solution Approach 1:
The patent implements a feedback mechanism where the function block continuously monitors its global counter synchronization status against the external IC's timer values through the shared register space. When jitter causes drift beyond a threshold, the system automatically triggers a resynchronization sequence to realign the counters. This closed-loop feedback ensures long-term synchronization stability despite short-term jitter variations inherent in global counter operations.
Solution Approach 2:
The patent allows dynamic adjustment of timer parameters including the ability to change the clock source and modify counter prescaler values. By changing these parameters, the system can optimize the global counter's behavior to reduce jitter effects in specific operating conditions, thereby improving synchronization stability while maintaining productive timing functions.
Data Source
AI summary
Various embodiments include methods and systems performed by a processor of a first function block for providing secure timer synchronization with a second function block. Various embodiments may include storing, in a shared register space, a first time counter value in which the first time counter value is based on a global counter of the second function block, transmitting, from the shared register space, the stored first time counter value to a preload register of the first function block, receiving, by the first function block, a strobe signal from the second function block configured to enable the first time counter value in the preload register to be loaded into a global counter of the first function block, and configuring the global counter with the first time counter value from the preload register.