Secure Programmable Timing Controller for Semiconductor ICs
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Solution Overview
Problem
The existing system controlling circuits for microcomputers face challenges in adapting to programmable specification changes due to the need for predefined sequences, which leads to extended development time and introduces security risks when allowing external CPU configuration.
Innovation Solution
A semiconductor integrated circuit with a programmable timing controller and a second boot programmable sequencer that adjusts system control signals and decrypts encrypted sequence codes to enable adaptable and secure specification changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a CPU is provided to enable free setting of registers for programmable specification change, then adaptability is improved, but security is worsened due to high risk of CPU takeover by third parties
Solution Approach 1:
The patent extracts the configuration functionality from an external CPU and implements it within the system controlling circuit itself through embedded sequencers and control logic. This allows the circuit to be reconfigured for different specifications without requiring an external CPU, thereby maintaining security while preserving adaptability.
Solution Approach 2:
The patent introduces an intermediate configuration mechanism that sits between the hardware implementation and the desired functionality. This intermediate layer allows specification changes to be made through controlled interfaces rather than direct CPU access, enabling adaptability while preventing unauthorized takeover attempts.
2Adaptability or versatility
If the number of selectable sequences is increased to adapt to elaborate control specifications, then adaptability is improved, but development TAT is worsened due to extended verification periods
Solution Approach 1:
The patent implements dynamic sequence selection capability where the system can adaptively choose from multiple predefined sequences based on operational requirements. The sequencer structure allows for programmable control of power supply, reset, and clock signals through different sequence combinations, enabling elaborate control specifications to be met without manually verifying each individual sequence.
Solution Approach 2:
The patent enables specification adaptation through parameter changes in the sequencer configuration rather than through structural modifications. By changing control parameters and sequence selection settings, the system can accommodate different specifications without requiring extensive re-verification, thereby reducing development TAT while maintaining adaptability.
Data Source
AI summary
A system controlling circuit disclosed herein is made adaptable to programmable specification change through parameters under a secure environment that is tamper resistant. A semiconductor integrated circuit including functional blocks and a system controlling circuit is configured as below. The system controlling circuit includes a programmable timing controller and a second boot programmable sequencer and supplies a group of system control signals including at least one of a power supply control signal, reset signal, and clock signal to the functional blocks. In the system controlling circuit, the programmable timing controller adjusts either or both of sequence and timing of supplying the group of system control signals to the functional blocks, based on parameters supplied thereto and the second boot programmable sequencer reads in encrypted sequence code and data, decrypts them, and supplies the programmable timing controller with the parameters in accordance with decrypted sequence code and data.