Secured Clock Synchronization via Validation Entity

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Solution Overview

Problem

Existing clock synchronization protocols in packet-compatible networks, such as PTP, are vulnerable to corruption or manipulation of timestamps, which can lead to accuracy degradation and denial of service, as they do not provide adequate security measures to validate the integrity of timing information during transmission.

Innovation Solution

Introducing a separate securing plane that validates timestamps and timing-related data before applying clock correction, ensuring that only validated information is used for synchronization tasks, and utilizing secured channels for message exchange between master and client clock nodes, as well as transparent clock nodes, to prevent manipulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If PTP protocol is used for clock synchronization in packet-compatible networks, then precise time, frequency and phase distribution is achieved, but timestamps may be corrupted or manipulated by intermediate malicious nodes

Engineering Contradiction:
Improvetime synchronization precisionVSAvoidtimestamp integrity
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent divides the synchronization system into separate functional planes: a data plane for transmitting PTP synchronization messages and a securing plane for validating timestamps. This segmentation allows the synchronization function to maintain precision while the security function independently ensures integrity through separate validation mechanisms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a validation entity as an intermediary component that sits between the master clock node and client clock nodes. This validation entity receives timestamps from the data plane, validates their integrity through the securing plane, and only accepts validated timestamps for synchronization, thereby preventing malicious manipulation while maintaining precise time distribution.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If security validation is added to verify timestamp integrity, then protection against malicious manipulation is improved, but system complexity increases

Engineering Contradiction:
Improvetimestamp validation securityVSAvoidsynchronization system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By segmenting the system into separate data plane and securing plane, the patent contains security validation functionality in a dedicated validation entity rather than embedding it throughout the entire synchronization system. This modular segmentation reduces overall system complexity while maintaining comprehensive security validation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The validation entity serves as a centralized intermediary that handles all security validation operations. By concentrating validation logic in this single component rather than distributing it across multiple nodes, the patent simplifies the overall system architecture while ensuring robust timestamp verification.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If timestamps are validated before clock correction, then accuracy degradation from malicious data is prevented, but synchronization processing time increases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidprocessing delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs security validation as a preliminary action before the clock correction step. The validation entity verifies timestamp integrity in advance, and only after successful validation does the clock node proceed with applying clock correction. This ordering ensures that malicious data is blocked before it can cause accuracy degradation, while the validation process itself is optimized to minimize overall processing time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12184407B2Secured clock synchronization in a packet-compatible network
Publication Date: 2024.12.31 ADTRAN NETWORKS SE
  • US12184407B2 patent drawing
  • US12184407B2 patent drawing
  • US12184407B2 patent drawing

AI summary

There is provided a technique of securing clock synchronization between master clock node (MCN) and client clock node (CCN). During a cycle of exchanging PTP messages between MCN and CCN, MCN generates an associated paired message for each PTP message generated thereby and informative of t1 or t4 timestamps provided by MCN and sends each paired message to a validation entity (VE) via a secured channel between MCN and VE. When PTP messages traverse transparent clock nodes (TCN) between MCN and CCN, each TCN generates a paired message for each version of PTP message updated thereby and sends each generated paired message to VE via a secured channel between respective TCN and VE. VE uses the received paired messages to provide a validation of the cycle, wherein synchronization-related task(s) (e.g. clock correction by the client clock node, etc.) are provided only subject to successful validation of the cycle by VE.