Security Chip Resisting SPA Attacks via Unified Arithmetic Unit
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Solution Overview
Problem
Existing security chips using RSA algorithms face challenges in resisting Simple Power Analysis (SPA) attacks and fault injection attacks due to the ability of attackers to differentiate between modular square and modular multiplication operations based on power consumption, leading to potential private key decipherment.
Innovation Solution
Implementing a method where the arithmetic unit performs both modular square and modular multiplication operations using the same hardware, with masking and unmasking operations using random numbers to obscure power consumption patterns, and incorporating a check mechanism to verify operation integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate hardware circuits are used for modular square and modular multiplication operations, then operation functionality is improved, but security against SPA attacks deteriorates
Solution Approach 1:
The patent merges the separate hardware circuits for modular square and modular multiplication operations into a single unified circuit. This unified circuit can perform both operations by interpreting control signals, thereby eliminating the distinguishable power consumption patterns that vulnerability SPA attacks while maintaining full operational functionality.
Solution Approach 2:
The patent designs a universal arithmetic unit that can perform multiple cryptographic operations (modular square, modular multiplication, and other arithmetic operations) through a single hardware structure controlled by different control signals. This multi-functional design ensures that the same hardware path is used for different operations, making power analysis attacks ineffective.
2Reliability
If masking operations with random numbers are implemented, then security against SPA attacks is improved, but device complexity increases
Solution Approach 1:
The patent introduces random numbers as intermediary elements that mask the actual cryptographic operations. These random numbers are added to intermediate results during computation, creating a statistical mask that prevents attackers from distinguishing operation types through power analysis, while the underlying unified circuit structure keeps the added complexity manageable.
3Reliability
If check mechanism is added to detect fault injection attacks, then security is improved, but operation time increases
Solution Approach 1:
The patent implements a feedback-based verification mechanism where the correctness of cryptographic operations is continuously checked during computation. The verification results are fed back to control whether the final output is released, enabling detection of fault injection attacks while minimizing time overhead by performing checks incrementally rather than adding significant sequential delay.
Data Source
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AI summary
Embodiments of the present invention disclose an operation method. The method is applied to a security chip, the security chip includes an input/output interface, a decryption circuit, a microprocessor, and an arithmetic unit. The method includes: obtaining, by the input/output interface, an input ciphertext; performing, by the decryption circuit, a modular exponentiation operation according to the ciphertext and a preset operation parameter; and using, by the microprocessor, an operation result obtained after the modular exponentiation operation as a plaintext obtained after decryption. The performing, by the decryption circuit, a modular exponentiation operation according to the ciphertext and a preset operation parameter is specifically: breaking, by the decryption circuit, the modular exponentiation operation into multiple iterative first operations, where the first operation is a modular square operation or a modular multiplication operation; sending, by the decryption circuit, the ciphertext and the operation parameter to the arithmetic unit; and performing, by the arithmetic unit, the first operation according to the ciphertext and the operation parameter to obtain a modular square value or a modular multiplication value. Correspondingly, the embodiments of the present invention further disclose a security chip. According to the present invention, an SPA attack can be resisted and security can be improved.