Security Control Circuit Clock Scaling Against Voltage Tampering
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Solution Overview
Problem
Existing security control circuits in FPGA integrated circuits, such as the Stratix 10, are vulnerable to voltage tampering attacks that can cause timing violations and compromise security functions, leading to potential data theft from secured regions.
Innovation Solution
A voltage monitoring circuit system that compares the supply voltage to a threshold voltage, adjusting the clock signal frequency to prevent timing violations without resetting the Security Device Manager (SDM), allowing the circuit to continue functioning during low supply voltage conditions caused by noise or attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SDM is reset when supply voltage drops below threshold to prevent timing violations, then security function reliability is improved, but system operation continuity deteriorates
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable based on supply voltage conditions. Instead of a fixed reset approach, the system dynamically adapts the clock frequency to match the actual operating voltage, allowing the SDM to continue operating securely even during voltage fluctuations without interruption.
Solution Approach 2:
The patent changes the clock signal frequency parameter in response to supply voltage variations. When voltage drops below the threshold, the clock frequency is reduced proportionally, ensuring that timing requirements are met at the lower voltage while maintaining continuous operation. This parameter adjustment resolves the contradiction by allowing reliable security functions without interrupting system operation.
2Reliability
If the clock signal frequency is reduced when supply voltage drops below threshold, then timing violation risk is reduced, but security function performance deteriorates
Solution Approach 1:
The patent adjusts the clock signal frequency parameter based on supply voltage levels. When voltage drops, the clock frequency is reduced to maintain timing compliance, but the system continues operating without reset. This controlled parameter change balances timing requirements with continued functionality, avoiding the performance loss that would result from a complete reset while ensuring timing violations are prevented.
Solution Approach 2:
The system uses feedback from voltage monitoring to continuously adjust the clock signal frequency. The monitoring circuit detects supply voltage levels and provides feedback that triggers appropriate clock frequency adjustments, ensuring timing compliance is maintained while minimizing impact on security function performance through adaptive rather than static control.
3Measurement precision
If a comparator-based voltage monitoring system is implemented, then voltage tampering detection capability is improved, but device complexity increases
Solution Approach 1:
The patent implements a self-service approach where the voltage monitoring circuit automatically triggers clock frequency adjustments without external intervention. The comparator-based system continuously monitors supply voltage and autonomously controls the clock signal generation, eliminating the need for complex external control logic or manual intervention while maintaining precise voltage tampering detection capability.
Solution Approach 2:
The patent uses the clock signal as an intermediary between the voltage monitoring circuit and the SDM. Instead of directly controlling complex security functions or resetting the SDM, the system mediates through clock frequency adjustment, which indirectly but effectively controls timing compliance and security operation in response to voltage conditions, simplifying the overall control architecture.
Data Source
AI summary
An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.