Security Co-Processor Migration of Trusted Attributes
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Solution Overview
Problem
Modern processors face challenges in efficiently executing complex instructions and managing sensitive security attributes in System on Chip (SoC) architectures, particularly in multiprocessor systems where secure assets need to be protected from unauthorized access.
Innovation Solution
The implementation of a processing apparatus that migrates trusted security attributes from a host CPU to a security engine co-processor, utilizing out-of-order processors and secure attribute management mechanisms to restrict access to secure assets and ensure exclusive access by the security engine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If security attributes are managed on the host CPU, then ease of operation is improved, but security reliability deteriorates due to potential unauthorized access
Solution Approach 1:
The system segments security attribute management from the host CPU by introducing a dedicated security co-processor. The host CPU retains general processing functions while the security co-processor handles exclusive security attribute operations, achieving both ease of operation through specialized handling and improved reliability through physical separation of security functions.
Solution Approach 2:
The security co-processor acts as an intermediary between the host CPU and secure assets. It receives requests from the host CPU, validates them against security attributes, and controls access to secure assets, thereby maintaining ease of operation for the host while ensuring robust security through an intermediate verification layer.
2Reliability
If a security co-processor is introduced, then security reliability is improved, but device complexity increases
Solution Approach 1:
The security co-processor is designed with multi-functionality to handle various security operations including attribute validation, access control decisions, and secure asset management. This universal security handling capability reduces the need for multiple specialized security components, thereby improving reliability while controlling the increase in device complexity.
3Reliability
If secure assets are isolated from host CPU, then security reliability is improved, but ease of operation deteriorates due to restricted access
Solution Approach 1:
The security co-processor serves as an intermediary that maintains isolation of secure assets from the host CPU while providing controlled access. It validates access requests against security attributes and grants access when appropriate, thereby maintaining security reliability through isolation while preserving ease of operation through automated access control.
4Productivity
If multiple processors share secure assets, then productivity is improved through parallel processing, but security reliability deteriorates due to access control challenges
Solution Approach 1:
The system segments security attribute management from the host CPU by introducing a dedicated security co-processor. The host CPU retains general processing functions while the security co-processor handles exclusive security attribute operations, achieving both ease of operation through specialized handling and improved reliability through physical separation of security functions.
Solution Approach 2:
The security co-processor autonomously validates access requests from multiple processors against security attributes without requiring host CPU intervention. This self-service security validation enables multiple processors to access secure assets in parallel while maintaining security reliability through independent, dedicated security checking.
Data Source
AI summary
A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.