Security Windows for Synchronization Pulse Timing Alignment
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Solution Overview
Problem
In multi-chip systems, slight variations in count frequencies between chips can cause their system counts to drift apart over time, leading to mismatches that create problems for software executing on the computing system.
Innovation Solution
The implementation of cooperative timing alignment techniques, where a synchronization signal is generated to align the system counts of different chips. This synchronization signal comprises synchronization pulses, which chips use to set their system counts to match implied system counts, thereby aligning their timings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chips operate independently with their own local timing signals, then each chip can function autonomously, but system count drift occurs between chips over time
Solution Approach 1:
The patent implements a feedback mechanism where a reference clock signal is distributed to all chips, and each chip's count controller continuously compares its local system count against the reference clock. This feedback loop allows chips to autonomously adjust their timing to maintain synchronization with the reference, resolving the contradiction between chip autonomy and system count synchronization.
Solution Approach 2:
The patent creates a common timing reference potential by distributing the reference clock signal to all chips in the multi-chip system. This equipotential approach ensures that all chips operate from the same timing baseline, eliminating drift while preserving individual chip autonomy through their independent count controllers that reference this common signal.
2Reliability
If synchronization pulses are transmitted without security measures, then timing alignment is achieved, but the system becomes vulnerable to malicious attacks
Solution Approach 1:
The patent applies preliminary anti-action by implementing security windows that preemptively define acceptable arrival time ranges for synchronization pulses before attacks can occur. The count controller checks whether received pulses fall within these pre-established security windows, and rejects pulses that arrive outside the window, thereby preventing malicious timing attacks before they can disrupt system synchronization.
Solution Approach 2:
The patent introduces security windows as an intermediary mechanism between the synchronization pulse transmission and the timing alignment function. This intermediary layer validates pulses against security criteria (arrival within expected time window) before allowing them to affect system timing, thus protecting the timing alignment function from malicious attacks while maintaining its operational integrity.
Data Source
AI summary
Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.