SED Parity Erasure Correction for MLC Flash ECC Codewords
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Solution Overview
Problem
Multi-Level Cell (MLC) flash memory devices experience increased bit error rates due to merging of threshold voltage distribution profiles, leading to unreliable data storage and erasures, which existing error correction methods struggle to effectively address.
Innovation Solution
Implementing single error detection (SED) parity bits and soft read information to correct erasures prior to ECC decoding, allowing for a reduced number of bit errors in the ECC codeword, thereby enhancing error correction capability and extending the useful life of data storage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory devices store multiple bits per cell to increase storage density, then storage density is improved, but bit error rate increases due to merging of threshold voltage distribution profiles
Solution Approach 1:
The patent segments the error correction process into two distinct stages: first using SED parity bits to detect and correct single bit errors, then using ECC parity bits to correct remaining errors. This segmentation allows each correction mechanism to be optimized for its specific function, improving overall reliability while maintaining storage density.
Solution Approach 2:
The patent performs preliminary error correction using SED parity bits before applying ECC decoding. By detecting and correcting single bit errors in advance, the system reduces the burden on the ECC decoder and improves the overall error correction capability, thereby enhancing reliability without sacrificing storage density.
2Reliability
If traditional ECC parity bits are used for error correction, then error correction capability is provided, but the capability is limited compared to the proposed SED parity bit approach
Solution Approach 1:
The patent divides the parity bit structure into two segments: SED parity bits for single error detection and correction, and ECC parity bits for broader error correction. This segmentation enables the system to achieve superior error correction capability by combining the strengths of both approaches, while the modular structure manages complexity effectively.
Solution Approach 2:
The SED parity bits act as an intermediary layer between the stored data and the ECC decoding process. They provide preliminary error detection and correction, serving as a mediator that prepares the data for more comprehensive ECC processing, thereby enhancing overall error correction capability.
3Measurement precision
If soft read operations are performed at offset voltages to detect erasures, then erasure detection is improved, but additional read operations increase time consumption
Solution Approach 1:
The patent performs soft read operations at offset voltages as a preliminary step to identify potential erasures before committing to full error correction procedures. This preliminary detection mechanism improves measurement precision by accurately identifying erasures, while the early detection allows for more efficient subsequent processing that minimizes time loss.
Data Source
AI summary
A method includes receiving a representation of a set of single error detection (SED) parity bits and a representation of data. The data includes an error correction coding (ECC) codeword including information bits and ECC parity bits. Each SED parity bit of the set of SED parity bits indicates a parity value for a corresponding portion of the data. The method includes, in response to determining that a particular portion of the representation of the data includes a single erasure bit, selectively modifying a bit value of the single erasure bit based on the representation of the SED parity bit that corresponds to the particular portion and generating an updated representation of the ECC codeword when the bit value of the single erasure bit corresponds to the ECC codeword and has been modified. The method may include initiating an ECC decode operation of the updated representation of the ECC codeword.