Seed Generating Circuit With Smoothing for Balanced Random Bits
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Solution Overview
Problem
Existing pseudo random number generating circuits fail to produce high-quality random numbers with balanced '0' and '1' frequencies and lack mechanisms to prevent periodicity and regularity in data sequences, especially when using the same system clock, due to dependence on initial seed values and difficulty in rewriting seeds to ensure randomness.
Innovation Solution
A seed generating circuit comprising an oscillating circuit, a smoothing circuit, and a postprocessing circuit that generates a one-bit seed by controlling the appearance frequencies of '0' and '1' in digital data sequences, using an intermittent oscillating circuit and XOR operations to improve randomness and balance, while minimizing circuit size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a pseudo random number generating circuit is used, then the circuit size is small and time-sequence randomness is good, but the data sequence randomness (when sampling with same system clock) is not good and shows periodicity
Solution Approach 1:
The patent applies preliminary action by generating multiple candidate seed values before the main random number generation process. The seed generating circuit produces several candidate seeds, which are then evaluated and selected to ensure high-quality randomness in the data sequence while maintaining compact circuit size.
Solution Approach 2:
The patent uses an intermediary approach by introducing a seed generating circuit as a mediator between the system clock and the pseudo random number generating circuit. This intermediary circuit processes the clock signal to generate random seed values, thereby improving the data sequence randomness without significantly increasing the overall circuit size.
2Device complexity
If the seed is fixed in the pseudo random number circuit, then the circuit operation is simple, but the random number sequences obtained are always the same and lack randomness
Solution Approach 1:
The patent applies dynamics by making the seed value dynamic rather than fixed. The seed generating circuit continuously generates new seed values based on the system clock, ensuring that the pseudo random number circuit receives varying seeds and produces different random number sequences each time, thereby maintaining both simplicity and randomness.
Solution Approach 2:
The patent uses self-service by enabling the seed generating circuit to automatically generate random seed values using the existing system clock without requiring external intervention. This self-service mechanism ensures continuous randomness while keeping the circuit operation simple and autonomous.
3Adaptability or versatility
If the seed is rewritten using software at system start, then the seed changes, but it is almost impossible to give the seed always different randomness and the balance of '0' and '1' shifts
Solution Approach 1:
The patent replaces the software-based seed rewriting mechanism with a hardware-based seed generating circuit. This hardware circuit directly processes the system clock signal to generate random seed values, eliminating the limitations of software rewriting and ensuring consistent randomness balance with equal distribution of '0' and '1'.
Solution Approach 2:
The patent applies parameter changes by transforming the seed generation process from a software-controlled parameter change to a hardware-based physical process. The seed generating circuit changes the seed values through physical clock signal processing, ensuring that the randomness parameters (balance of '0' and '1') remain consistent and reliable.
Data Source
AI summary
A random number generating circuit comprises: the seed generating circuit which generates a seed; and a pseudo random number circuit which generates pseudo random numbers based on the seed generated by the seed generating circuit. The seed generating circuit has: an oscillating circuit which oscillates continuously or intermittently, and which outputs a digital data sequence; a smoothing circuit which outputs time series data by controlling appearance frequencies of “0” and “1” in the digital data sequence outputted from the oscillating circuit; and a postprocessing circuit which generates one-bit seed by a computation using a plurality of bits included in the time series data.