Printed Wiring Board Seed Layer Geometry for Width-Controlled Circuits
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Solution Overview
Problem
Existing printed wiring boards face challenges in achieving precise control over the width and thickness of conductor layers and via conductors, leading to issues with adhesion and electrical resistance, particularly due to uneven surfaces and inconsistent etching rates during manufacturing.
Innovation Solution
The implementation of a structured seed layer with a first layer having a greater width than a second layer, and an electrolytic plating layer with an even wider width, combined with a smooth inner wall surface formed by controlled etching of inorganic particles, ensures precise conductor layer formation and improved adhesion, reducing electrical resistance and stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional single-layer seed layer is used, then the manufacturing process is simple, but the control over conductor width and thickness is imprecise
Solution Approach 1:
The seed layer is divided into two distinct layers: a first seed layer and a second seed layer. The first seed layer has a first width and the second seed layer has a second width that is smaller than the first width. This segmentation allows independent control of each layer's dimensions, enabling precise control over the final conductor width and thickness that cannot be achieved with a single-layer seed layer.
2Manufacturing precision
If the conductor layer width is reduced to achieve finer circuits, then the circuit density increases, but the adhesion and electrical resistance become problematic
Solution Approach 1:
The segmented two-layer seed layer structure enables the first seed layer to provide a wider base for better adhesion and the second seed layer to define the narrower final conductor width. This separation of functions allows fine conductor circuits to be formed while maintaining adequate adhesion and electrical properties through the wider first layer.
Solution Approach 2:
Different regions of the seed layer structure are given different widths and properties: the first seed layer has a larger width optimized for adhesion and electrical connection, while the second seed layer has a smaller width optimized for the final conductor dimensions. This local differentiation of properties allows simultaneous optimization of adhesion and conductor precision.
3Ease of manufacture
If etching is used to form via openings, then the via conductors are formed, but the surface becomes uneven and causes stress concentration
Solution Approach 1:
The via openings are formed by etching the resin insulating layer before the conductor layers are deposited. By performing this etching operation in advance, the subsequent plating process can fill the pre-formed openings without requiring additional etching steps that would create surface unevenness. This preliminary action separates the via formation from the conductor formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of conductor circuits with controlled widths and reduced electrical resistance, enhancing connection reliability and stress management, while maintaining a smooth surface finish.
Implementation Method 1
a second conductor layer formed on a surface of the resin insulating layer and including a conductor circuit, and a via conductor formed in an opening formed in the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer. The second conductor layer and the via conductor include a seed layer and an electrolytic plating layer formed on the seed layer
Data Source
AI summary
A printed wiring board includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the insulating layer and including a conductor circuit, and a via conductor formed in an opening formed in the insulating layer and connecting the first and second conductor layers. The second conductor layer and via conductor include a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer has a first layer and a second layer formed on the first layer, the first layer has a width greater than a width of the second layer in cross section of the conductor circuit in the second conductor layer and that the electrolytic plating layer has a width greater than the width of the first layer in cross section of the conductor circuit in the second conductor layer.


