Seed Layer Circuit Testing for Higher Electronic Device Yield
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Solution Overview
Problem
The challenge in manufacturing electronic devices is to enhance their reliability while improving yield and reducing costs, which existing methods have not adequately addressed.
Innovation Solution
A method involving the formation of a substrate with distinct regions, a seed layer, and a circuit structure layer, where a circuit test process applies voltage to test circuit structures to ensure connectivity and functionality, reducing waste and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used, then production speed is maintained, but reliability of electronic devices is insufficient
Solution Approach 1:
The patent applies preliminary action by forming a seed layer on the substrate before forming the circuit structure layer. This seed layer serves as a foundation that ensures proper electrical connections are established in advance, allowing for reliable device operation while maintaining manufacturing efficiency. The seed layer is prepared beforehand to prevent connection issues during subsequent manufacturing steps.
Solution Approach 2:
The patent implements feedback through a circuit test process that applies a predetermined voltage to test circuit structures. This testing mechanism provides feedback on whether circuit structures are normal, allowing for real-time quality verification. The feedback loop ensures that only properly connected devices proceed to production, thereby improving reliability without significantly impacting productivity.
2Loss of substance
If conventional testing methods are used, then manufacturing speed is maintained, but chip wastage due to manufacturing defects is high
Solution Approach 1:
The patent performs circuit testing at an earlier stage in the manufacturing process, before final device assembly. By applying predetermined voltage to test circuit structures while they are still on the substrate, the method identifies defective chips early, allowing for targeted removal or rework. This preliminary testing reduces chip wastage by preventing defective units from proceeding through subsequent manufacturing steps.
Solution Approach 2:
The testing process utilizes the device's own circuit structures and seed layer to perform self-testing. The predetermined voltage is applied through the seed layer to test the circuit structures themselves, allowing the device to verify its own functionality. This self-service approach eliminates the need for separate external testing equipment and reduces material waste.
Data Source
AI summary
A method for manufacturing an electronic device includes the following steps. A substrate including a first region and a second region is provided. A seed layer is formed on the substrate. A circuit structure layer is formed on the seed layer, and the circuit structure layer has a plurality of first circuit structures disposed on the first region and a plurality of second circuit structures disposed on the second region. The first circuit structures and the second circuit structures are electrically connected through the seed layer. A circuit test process is performed and includes applying a predetermined voltage to the second circuit structures to test the first circuit structures to determine whether the first circuit structures are normal or not.