Semiconductor Package Seed Layer Etching for Fine Line Integrity

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Solution Overview

Problem

The miniaturization of semiconductor packages has led to challenges in maintaining the reliability of line and space patterns due to potential short circuit defects and damage from excessive etching.

Innovation Solution

A method of manufacturing semiconductor packages involves forming seed layers with different metal materials, creating conductive patterns, and etching these layers using a specific etchant composition that includes fluorine ions, negative ions for competing reactions, and a corrosion inhibitor, to achieve controlled etching rates and prevent excessive etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching methods are used on miniaturized seed layers, then etching speed is maintained, but excessive etching occurs causing line pattern damage and short circuit defects

Engineering Contradiction:

Improveline pattern integrityVSAvoidetching speed

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent changes the chemical parameters of the etching solution by incorporating specific compounds (benzotriazole or imidazole) that modify the etching characteristics. These additives reduce the etching speed to prevent excessive etching while maintaining sufficient etching capability to form the required patterns, thereby resolving the contradiction between etching precision and productivity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces benzotriazole or imidazole as intermediary substances that mediate between the etching solution and the seed layer. These intermediaries control the etching reaction rate and prevent direct aggressive etching that would cause line pattern damage, thus protecting the patterns while still allowing controlled etching to proceed

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If etching is performed to form patterns, then conductivity pathways are created, but short circuit defects occur due to excessive etching

Engineering Contradiction:

Improveshort circuit preventionVSAvoidpattern definition

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent modifies the etching solution parameters by adding benzotriazole or imidazole compounds that control the etching rate. This parameter change ensures that etching stops at the appropriate depth to define patterns clearly without penetrating too deep and creating short circuits between adjacent conductive regions

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs a feedback mechanism where the etching solution composition is designed to self-regulate the etching process. The benzotriazole or imidazole compounds provide chemical feedback that slows down etching as it progresses, preventing over-etching and short circuit defects while maintaining adequate pattern definition

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the reliability of miniaturized line and space patterns by preventing short circuit defects and maintaining the integrity of the patterns, thereby improving the overall performance and durability of semiconductor packages.

Implementation Method 1

etching the first seed layer includes etching with an etchant that includes deionized water, a fluorine compound, a competing compound, and a corrosion inhibitor

Methodology Applied

Scientific EffectWet etching:

Implementation Method 2

etching the first seed layer includes etching with an etchant that includes fluorine ions and negative ions that undergo a negative ion competing reaction against the fluorine ions

Methodology Applied

Scientific EffectChemical reaction with fluorine ions:

Implementation Method 3

etching with an etchant that includes fluorine ions and negative ions that undergo a negative ion competing reaction against the fluorine ions

Methodology Applied

Scientific EffectNegative ion competing reaction:

Implementation Method 4

etching with an etchant that includes deionized water, a fluorine compound, a competing compound, and a corrosion inhibitor

Methodology Applied

Scientific EffectCorrosion inhibition:

Data Source

PatentUS12300509B2Method of manufacturing semiconductor package

Publication Date: 2025.05.13 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of manufacturing a semiconductor package, the method including providing a first seed layer on an insulation layer such that the first seed layer includes a first metal material; providing a second seed layer on the first seed layer such that the second seed layer includes a second metal material different from the first metal material; forming photoresist patterns on the second seed layer; forming conductive patterns between the photoresist patterns, including the second metal material, and having line shapes that extend in a first direction; removing the photoresist patterns; etching the second seed layer to form second seed patterns having line shapes extending in the first direction; and etching the first seed layer to form first seed patterns having line shapes extending in the first direction, wherein an etchant includes deionized water, a fluorine compound, a competing compound, and a corrosion inhibitor.