Seed Metal Layer as Interconnect for Semiconductor Manufacturing

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Solution Overview

Problem

Conventional methods for manufacturing semiconductor devices result in increased costs due to the removal of ultra-thin copper foils as waste and degrade the planarity of interconnect layers due to uneven patterns on transfer substrates.

Innovation Solution

A method involving the formation of a seed metal layer on a supporting substrate, followed by the creation of an interconnect layer and subsequent patterning of the seed metal layer to form a second interconnect, allowing the seed metal layer to be utilized as an interconnect without additional metal layers, thus maintaining planarity and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the ultra-thin copper foil is removed from the interconnect layer, then the supporting substrate can be separated, but the copper foil becomes waste and manufacturing cost increases

Engineering Contradiction:
Improvesubstrate separationVSAvoidcopper foil waste
Core Design Contradiction:
Ease of manufactureVSLoss of substance

Solution Approach 1:

The patent applies the discarding and recovering principle by preventing the copper foil from becoming waste through the peeling process. Instead of removing the copper foil as waste, the invention designs the peeling process to separate only the supporting substrate while retaining the copper foil as a reusable resource that can be recovered and utilized in subsequent manufacturing steps

Inventive Principle:
Principle #34Discarding and recovering

2Ease of manufacture

If a patterned interconnect is formed on the transfer substrate, then the interconnect can be sealed in resin, but the planarity of the interconnect layer is degraded due to unevenness

Engineering Contradiction:
Improveinterconnect sealingVSAvoidinterconnect layer planarity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies the preliminary action principle by forming the interconnect pattern on the transfer substrate before the peeling process. This preliminary patterning allows the interconnect to be precisely defined and then sealed in resin, while the subsequent peeling of the supporting substrate does not affect the already-formed interconnect pattern or its planarity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8058165B2Semiconductor device and method of manufacturing the same
Publication Date: 2011.11.15 RENESAS ELECTRONICS CORP
  • US8058165B2 patent drawing
  • US8058165B2 patent drawing
  • US8058165B2 patent drawing

AI summary

A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.