SEG Conductive Layer for Vertical NVM Parasitic Capacitance
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Solution Overview
Problem
Traditional vertical channel NVM devices face increased power consumption and reduced reliability due to parasitic junction capacitance and signal interference caused by the high resistance doped region in the semiconductor substrate serving as the bottom common source line.
Innovation Solution
A memory device with a semiconductor substrate, a bottom insulating layer, and a selective epitaxial growth (SEG) conductive layer as the bottom common source line, reducing the current path length and eliminating parasitic junction capacitance by using a contact plug to electrically connect the substrate directly to the conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a doped region is used as the bottom common source line in the semiconductor substrate, then the memory device can be fabricated with traditional processes, but the operation resistance increases and parasitic junction capacitance causes signal interference
Solution Approach 1:
An undoped semiconductor layer is introduced as an intermediary between the doped region and the channel layer. This intermediary layer acts as a buffer that prevents direct interaction between the doped region and channel, thereby eliminating parasitic junction capacitance while maintaining compatibility with traditional fabrication processes. The undoped layer serves as a mediator that decouples the electrical interference from the structural connection.
Solution Approach 2:
The bottom common source line is segmented into two distinct parts: a doped region for electrical connection and an undoped semiconductor layer for signal isolation. This segmentation separates the functions of electrical conduction and signal transmission, allowing the doped region to provide low-resistance connection while the undoped layer prevents parasitic capacitance formation with the channel.
2Device complexity
If a doped region serves as the bottom common source line, then the device structure is simple, but the power consumption increases due to high resistance
Solution Approach 1:
The bottom common source line is divided into a doped region and an undoped semiconductor layer. The doped region provides low-resistance electrical connection to reduce power consumption, while the undoped layer maintains structural simplicity by being integrated into the existing substrate without adding complex external components.
Solution Approach 2:
The doping concentration parameter is changed along the vertical direction: high doping in the bottom region for low resistance and zero doping in the upper layer for signal isolation. This parameter gradient allows simultaneous optimization of electrical conductivity and parasitic capacitance reduction, addressing both power consumption and structural complexity requirements.
3Ease of manufacture
If a doped region is used for the bottom common source line, then the device can be fabricated with standard processes, but parasitic junction capacitance causes RC delay
Solution Approach 1:
The undoped semiconductor layer serves as a mediator that breaks the direct capacitive coupling between the doped region and the channel. This intermediary structure eliminates the parasitic junction capacitance that causes RC delay, thereby improving device speed while maintaining compatibility with standard fabrication processes that can form undoped layers through selective epitaxial growth or implantation.
Solution Approach 2:
The undoped semiconductor layer is formed in advance during the fabrication process, before the channel layer is deposited. This preliminary action ensures that the parasitic capacitance prevention structure is already in place when the channel is formed, eliminating RC delay from the outset without requiring additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces operation resistance and improves reliability and speed by eliminating parasitic junction capacitance and signal interference, with the SEG conductive layer providing lower resistance and better conductivity compared to traditional poly-silicon layers.
Implementation Method 1
a selective epitaxial growth (SEG) conductive layer as the bottom common source line
Data Source
AI summary
A memory device includes a semiconductor substrate, a bottom insulating layer disposed on the semiconductor substrate, a first conductive layer which is a selective epitaxial growth layer disposed on the bottom insulating layer; a plurality insulating layers disposed over the bottom insulating layer; a plurality of second conductive layers alternatively stacked the insulating layers and insulated from the first conductive layer; a contact plug passing through the bottom insulating layer and electrically contacting the semiconductor substrate with the first conductive layer; a channel layer disposed on at least one sidewall of at least one first through opening and electrically contact the contact plug, wherein the first through opening passes through the insulating layers, the second conductive layers, so as to expose the contact plug; and a memory layer disposed between the channel layer and the second conductive layers.