Segment Divider Circuit for High-Frequency Large Bit Width Division
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital signal processing technologies face challenges in efficiently performing division operations, especially with large bit widths, leading to reduced frequencies and increased complexity in divider circuitry.
Innovation Solution
A segment divider circuit and method that uses cascaded shift registers, calculators, and control circuits to perform division operations segment by segment through shift, comparison, and subtraction, improving frequency support and simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional divider circuit is used to perform division operations with large bit widths, then the division operation can be completed, but the operating frequency decreases and the circuit complexity increases
Solution Approach 1:
The patent divides the dividend data into multiple segments (first dividend segment, second dividend segment, etc.) and processes each segment separately through cascaded calculators. This segmentation allows the division operation to be broken down into smaller, manageable stages that can operate in parallel or sequence, improving overall processing speed while keeping each individual calculator unit relatively simple in structure.
2Adaptability or versatility
If the bit width of the divider circuit is increased to handle larger data, then the processing capability is improved, but the highest supported frequency decreases
Solution Approach 1:
The patent segments both the dividend and divisor data into multiple parts (first dividend segment, second dividend segment, first divisor segment, second divisor segment). Each segment is processed by dedicated calculator units, allowing the system to handle large bit widths through modular processing rather than requiring a single large complex unit, thereby maintaining higher operating frequencies.
Solution Approach 2:
The patent introduces a time dimension by processing different segments in sequential stages through cascaded calculators. Instead of processing all bits simultaneously in a single stage, the division operation is distributed across multiple time steps with each calculator handling specific segment combinations, effectively trading spatial complexity for temporal processing.
3Productivity
If a single-stage divider circuit is used, then the circuit structure is compact, but it cannot efficiently handle large bit width division operations
Solution Approach 1:
The patent divides the division operation into multiple stages with cascaded calculators, where each calculator processes specific segments of the dividend and divisor. This multi-stage segmented approach enables efficient handling of large bit widths by breaking down the complex single-stage operation into simpler sequential steps, improving efficiency without requiring an overly complex monolithic structure.
Solution Approach 2:
The patent employs dynamic control signals (first control signal, second control signal, third control signal) to manage the operation of different calculator stages and shift register circuits. This dynamic control allows the circuit to adapt its operation mode based on the data being processed, enabling efficient large bit width division while maintaining reasonable structural complexity through controlled activation of different circuit components.
Data Source
AI summary
A segment divider, a segment division operation method, and an electronic device are disclosed, relating to the technical field of digital signal processing. The divider includes: a first shift register circuit; a second shift register circuit; a calculation circuit configured to compare data in first registers and data in second registers according to the cascade order, to perform a preset operation and generate an operation result; a third shift register circuit configured to receive and register the operation result bit by bit; then a shift control circuit configured to control the first shift register circuit and the third shift register circuit to perform a shift operation; a counting circuit configured to accumulate the number of shift operations after each shift operation, and send an output signal to finish the operation or send a calculation signal to continue the operation; and an output circuit configured to output a target result.