Segmented ADC Circuit for CDAC Mismatch Linearity
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in achieving precise and accurate conversion of analog signals due to nonlinearity errors caused by capacitor mismatch in capacitive digital-to-analog converters (CDACs), which can result in deviations from desired statistical properties and increased nonlinearity.
Innovation Solution
The ADC derives a first code approximating the combination of an analog input value and a dither value, then uses a second code to represent the residue, combining these codes to improve linearity by applying them to a capacitor array, thereby reducing the impact of capacitor mismatch errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional binary-weighted encoding is used in CDAC, then the ADC structure is simple, but capacitor mismatch causes nonlinearity errors and degraded measurement precision
Solution Approach 1:
The patent divides the capacitor array into multiple segments (first segment and second segment) with different encoding schemes. The first segment uses binary-weighted encoding while the second segment uses non-binary-weighted encoding (such as thermometer encoding). This segmentation allows each segment to contribute differently to the final digital output, improving linearity by reducing the impact of capacitor mismatch errors while maintaining a manageable overall structure.
2Measurement precision
If capacitor mismatch is present in CDAC, then manufacturing is easier, but nonlinearity errors increase and conversion accuracy deteriorates
Solution Approach 1:
The patent changes the encoding parameter from conventional binary-weighted encoding to include non-binary-weighted encoding in at least one segment of the capacitor array. This parameter change in the encoding scheme makes the ADC more robust against capacitor mismatch by reducing the sensitivity of the conversion accuracy to variations in capacitor values, thereby improving conversion accuracy even when manufacturing tolerances cause mismatch.
3Measurement precision
If binary-weighted encoding is used, then the digital output structure is simple, but nonlinearity errors deviate from desired statistical properties
Solution Approach 1:
The patent segments the capacitor array into multiple parts with different encoding schemes. The first segment uses binary-weighted encoding for simplicity while the second segment uses non-binary-weighted encoding to improve statistical properties. The digital output is formed by combining outputs from both segments, achieving desired statistical properties for nonlinearity errors while maintaining reasonable structural complexity.
Data Source
AI summary
Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.