Segmented ADC Stage With Parallel DAC Slices for Low-Noise Speed
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Solution Overview
Problem
Analog to digital converters face challenges in achieving high speed and resolution while maintaining good noise performance, as smaller sampling capacitors reduce thermal noise but increase thermal noise, and larger capacitors improve noise performance but slow down conversion rates.
Innovation Solution
The use of multiple DAC slices with small capacitance for fast conversion and larger capacitance for improved thermal noise, where each slice has matched RC time constants and transistor switches to minimize timing skew, allowing for parallel operation to form a residue with reduced thermal noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If smaller sampling capacitors are used, then conversion speed is improved, but thermal noise performance deteriorates
Solution Approach 1:
The ADC stage is divided into multiple parallel slices, each with its own sampling capacitor. By segmenting the total capacitance into multiple smaller capacitors operating in parallel, the patent achieves fast conversion speed (each capacitor can be small) while maintaining good thermal noise performance (the combined effect of multiple capacitors). Each slice processes a portion of the signal simultaneously, and the results are combined to form the final output.
2Object-generated harmful factors
If larger sampling capacitors are used, then thermal noise performance is improved, but conversion speed deteriorates
Solution Approach 1:
Instead of using one large sampling capacitor that would slow down conversion, the patent segments the capacitance into multiple smaller capacitors arranged in parallel. Each small capacitor contributes to the total effective capacitance while maintaining fast charging/discharging characteristics. The parallel arrangement ensures that the combined noise performance approaches that of a single large capacitor without the speed penalty.
3Measurement precision
If multiple DAC slices are used with matched RC time constants, then timing skew is minimized, but device complexity increases
Solution Approach 1:
Each DAC slice is designed with locally matched RC time constants, meaning that the resistance and capacitance values are carefully selected and matched within each slice to ensure uniform timing characteristics. This local matching approach minimizes timing skew across all slices without requiring complex global synchronization circuits. The transistor switches in each slice are also designed with matched characteristics to further reduce timing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed analog to digital conversion with improved thermal noise performance without sacrificing resolution, by using multiple slices with matched time constants and transistor switches to form a residue, effectively decoupling noise and speed issues.
Implementation Method 1
an acquisition circuit having a first time constant
Implementation Method 2
each comprising an acquisition circuit having substantially the same time constant as the first time constant
Data Source
AI summary
A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.