Segmented Adder Tree for Large-Integer Area and Latency Limits
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Solution Overview
Problem
Conventional adder circuits in integrated circuits, such as FPGAs, face challenges in performing large precision arithmetic operations due to significant area occupation, high power consumption, and latency issues, particularly in encryption and multiplication operations involving large precision operands.
Innovation Solution
A restructured adder network is implemented, where each adder node receives large inputs segmented into smaller parts, allowing independent computation of sums and carries, with a prefix network generating carry bits and a final adder stage combining sum and carry vectors to minimize latency and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If smaller adders are chained together to accommodate large precision arithmetic, then the adder circuit can perform large precision operations, but it occupies a substantial amount of area on the integrated circuit
Solution Approach 1:
The adder circuit is divided into multiple independent adder stages, each handling a specific segment of the large precision operation. These stages are organized in a tree-like structure where intermediate results are combined progressively, allowing the circuit to handle large precision arithmetic without requiring a single monolithic adder that would occupy excessive area.
2Measurement precision
If smaller adders are chained together to accommodate large precision arithmetic, then the adder circuit can perform large precision operations, but it consumes a relatively large amount of power
Solution Approach 1:
By segmenting the adder circuit into independent stages, power consumption is distributed and optimized at each stage rather than concentrated in a single large adder. This allows for more efficient power management and reduces overall power consumption while maintaining large precision capability.
3Measurement precision
If smaller adders are chained together to accommodate large precision arithmetic, then the adder circuit can perform large precision operations, but it introduces additional latency in the integrated circuit
Solution Approach 1:
The adder stages are organized in a tree structure where computations are performed in parallel at intermediate levels rather than sequentially chained. This allows preliminary additions to occur simultaneously, significantly reducing the overall latency compared to sequential chaining while maintaining the ability to handle large precision arithmetic.
Data Source
AI summary
An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.