Bottom-Barrier-Free Metal Interconnection via Segmented Barrier Layers
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices face challenges in forming robust metal interconnections with low via resistance, particularly due to the complexity of scaling down in IC processing and manufacturing.
Innovation Solution
A method involving the formation of a bottom-barrier-free metal interconnection scheme, where a first barrier layer is deposited in trenches and undergoes thermal treatment to form different barrier layers, allowing for selective etching and conformal deposition of via metal and metal layers, reducing via resistance and improving device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional barrier layer formation methods are used, then via resistance is high, but process complexity is low; if bottom-barrier-free metal interconnection is used, then via resistance is reduced, but process complexity increases
Solution Approach 1:
The barrier layer is segmented into two distinct portions: a first portion formed in the trench that prevents via resistance, and a second portion formed on the plug surface that enables selective etching. This segmentation allows each portion to serve its specific function independently, resolving the contradiction between reducing via resistance and maintaining process simplicity.
Solution Approach 2:
Different portions of the barrier layer are given different properties through selective etching. The first portion in the trench maintains its barrier properties to reduce via resistance, while the second portion on the plug surface is selectively removed to enable subsequent metal deposition. This local differentiation resolves the contradiction by providing tailored properties in different locations.
2Ease of manufacture
If thermal treatment is applied to convert barrier layer portions, then selective etching becomes possible, but manufacturing time increases
Solution Approach 1:
The thermal treatment is performed in advance to convert the barrier layer into two distinct portions with different etch selectivities. This preliminary action enables subsequent selective etching steps to proceed efficiently without requiring additional complex processing, thereby reducing overall manufacturing time despite the initial thermal treatment step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces via resistance, and enhances the reliability of semiconductor devices by limiting electron migration and time-dependent dielectric breakdown, while allowing for different deposition processes to suit the needs of various trench structures.
Implementation Method 1
a first barrier layer is deposited in trenches and undergoes thermal treatment to form different barrier layers
Implementation Method 2
conformal deposition of via metal and metal layers
Data Source
AI summary
A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.