Segmented Bit Line Architecture for Floating Body Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Floating body memory cell arrays face increased power consumption due to disturb voltages during read and write operations, which necessitate shorter refresh intervals and higher power usage.
Innovation Solution
The integration of isolation circuits between bit line segments and bit lines allows for selective coupling and decoupling, reducing voltage disturbances and enhancing control over memory cell operations, thereby optimizing power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating body memory cell arrays are used, then data storage capability is improved, but power consumption increases due to disturb voltages during read and write operations
Solution Approach 1:
The bit line is divided into multiple bit line segments, each associated with a specific group of memory cells. This segmentation allows selective coupling of only the relevant bit line segment to the sense amplifier during read/write operations, isolating other segments to minimize voltage disturbances and reduce power consumption while maintaining data storage capability.
Solution Approach 2:
Isolation circuits are introduced as intermediary components between bit line segments and the main bit line. These isolation circuits selectively couple or decouple bit line segments based on operational needs, acting as mediators that control voltage distribution and minimize unnecessary voltage disturbances, thereby reducing power consumption while preserving memory functionality.
2Productivity
If floating body memory cell arrays operate with disturb voltages, then read and write operations are enabled, but refresh intervals must be shortened increasing power usage
Solution Approach 1:
By segmenting the bit line into multiple isolated sections, voltage disturbances are confined to only the active segment during read/write operations. This prevents disturbance propagation to other segments, allowing longer refresh intervals between operations and reducing the frequency of power-intensive refresh cycles.
Solution Approach 2:
Isolation circuits serve as intermediaries that control the coupling between bit line segments. During read/write operations, they enable selective connection of the active segment while isolating others, thereby limiting voltage disturbance scope and extending the duration between required refresh operations.
3Reliability
If isolation circuits are integrated between bit line segments and bit lines, then voltage disturbance control is improved, but device complexity increases
Solution Approach 1:
The bit line is divided into multiple segments with isolation circuits positioned between them. This segmentation approach strategically places isolation components only where needed to control voltage disturbances, rather than throughout the entire circuit, thereby achieving effective disturbance control while minimizing the overall increase in device complexity.
Solution Approach 2:
Isolation circuits are introduced as intermediary components between bit line segments. These intermediaries provide precise control over voltage disturbance propagation with minimal impact on the overall device architecture, achieving reliable voltage control while maintaining relatively simple device structure through targeted placement.
Data Source
AI summary
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.