Segmented Memory Cell Bit Lines for Lower Sense Amplifier Power
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing power consumption and improving integration by optimizing the structure of memory cell arrays and bit line sense amplifiers.
Innovation Solution
The semiconductor memory device incorporates a segmented cell bit line structure with a bit line sense amplifier in a different layer, reducing capacitance and power consumption while utilizing a dummy cell array to utilize unpaired cell bit lines on the periphery, and includes edge and dummy bit line sense amplifiers to enhance capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cell bit line is made continuous to connect all memory cells, then the memory cell array can be fully accessed, but the capacitance of the cell bit line increases leading to higher power consumption in the bit line sense amplifier
Solution Approach 1:
The cell bit line is divided into multiple segments along its length, with isolation regions positioned at specific locations to electrically separate portions of the bit line. This segmentation reduces the total capacitance of the cell bit line, thereby reducing the power consumption of the bit line sense amplifier while maintaining full accessibility to all memory cells through controlled activation of specific segments
2Device complexity
If the memory cell array and bit line sense amplifier are placed in the same layer to simplify interconnection, then the device structure is simpler, but the integration density and capacity of the memory device are reduced
Solution Approach 1:
The bit line sense amplifier is moved from the same layer as the memory cell array to a different layer, creating a three-dimensional stacked structure. This vertical separation allows the memory cell array and sense amplifier to overlap in the planar view, significantly increasing the integration density and effective capacity of the memory device while maintaining simplified interconnections through vertical vias
3Device complexity
If unpaired cell bit lines on the periphery are discarded to simplify the structure, then the device structure is simpler, but the memory device capacity is reduced
Solution Approach 1:
Dummy cell arrays are extracted and positioned in the peripheral regions of the memory device, specifically designed to accommodate and utilize the previously discarded unpaired cell bit lines. These dummy arrays are connected to the unpaired bit lines through isolation regions, allowing these peripheral bit lines to be productively used for additional storage capacity rather than being left unused
Data Source
AI summary
A semiconductor memory device includes: a memory cell array located in a first layer and including a word line, a cell bit line, and a memory cell located in a region where the word line and the cell bit line are crossed; and a bit line sense amplifier located in a second layer, different from the first layer. The bit line sense amplifier is connected to a bit line that is connected to the cell bit line and to a complementary bit line corresponding to the bit line. The bit line sense amplifier detects data stored in the at least one memory cell. Each of the at least one cell bit line is segmented into two or more portions, and the two or more portions are respectively connected to the bit line and the complementary bit line connected to the bit line sense amplifier.