Segmented Bitline Circuit for Embedded Memory Speed
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Solution Overview
Problem
In deep submicron technology, there is a tradeoff between the capacity and access speed of memory, with higher capacity leading to slower access speeds, and existing solutions for improving dynamic logic circuits and power consumption are inadequate for achieving both high-speed and low-power embedded memory.
Innovation Solution
The proposed solution involves a circuit design with segmented bitlines, a precharge circuit, bitline keepers, and shutdown transistors, which reduces bitline capacitance and power consumption by partitioning the bitline into thirds, increasing the drive strength of pulldown transistors, and optimizing the placement of precharge transistors to speed up discharge times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bitline capacity is increased to support higher storage capability, then the storage capacity is improved, but the access speed becomes slower
Solution Approach 1:
The bitline is divided into multiple segments with bitline repeaters inserted at intermediate points. Each segment has its own precharge transistor and keeper circuit, allowing independent operation. This segmentation reduces the effective capacitance that each portion of the bitline must charge/discharge, thereby maintaining high access speed while supporting increased storage capacity through the extended bitline structure.
2Quantity of substance
If the bitline length is increased to support higher capacity, then the storage capacity is improved, but the power consumption increases
Solution Approach 1:
The bitline is divided into multiple segments with bitline repeaters inserted at intermediate points. Each segment has its own precharge transistor and keeper circuit, allowing independent operation. This segmentation reduces the effective capacitance that each portion of the bitline must charge/discharge, thereby maintaining high access speed while supporting increased storage capacity through the extended bitline structure.
Solution Approach 2:
Keeper circuits are strategically positioned at specific locations along the segmented bitline to maintain voltage levels only where needed. This localized approach ensures that only the necessary portions of the bitline consume power for maintaining data, rather than the entire bitline length, thus reducing overall power consumption while supporting higher capacity.
3Device complexity
If conventional bitline circuits are used without segmentation, then the device complexity is low, but the access speed and power efficiency are insufficient
Solution Approach 1:
The bitline is divided into multiple segments with bitline repeaters inserted at intermediate points. Each segment has its own precharge transistor and keeper circuit, allowing independent operation. This segmentation reduces the effective capacitance that each portion of the bitline must charge/discharge, thereby maintaining high access speed while supporting increased storage capacity through the extended bitline structure.
Solution Approach 2:
Precharge transistors are positioned to charge bitline segments to a predetermined voltage level before read operations. This preliminary action ensures that bitline segments are ready for rapid discharge during read operations, improving access speed without requiring complex dynamic control circuits.
Data Source
AI summary
A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output.