Segmented Programmable Capacitor Array for Leakage Reduction
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Solution Overview
Problem
Ferroelectric capacitors with high defect densities suffer from prohibitively high leakage currents, limiting their use in large area applications due to high defect densities in materials like Lead Zirconate Titanate (PZT) and Strontium Bismuth Titanate (SBT), which affect the reliability and efficiency of semiconductor integrated circuits.
Innovation Solution
A capacitor circuit that includes a plurality of transistors and capacitors, where a control circuit selectively connects and disconnects capacitors based on defect testing, ensuring only non-defective capacitors are connected in parallel, thereby minimizing leakage current and maximizing the use of high dielectric capacitors while conserving layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ferroelectric materials with high dielectric constant are used to increase capacitance, then capacitance density is improved, but leakage current increases due to high defect density
Solution Approach 1:
The capacitor array is divided into multiple individually addressable capacitor elements, each with its own defect profile. By segmenting the array, defective capacitors can be identified and excluded without affecting the entire array, allowing use of high dielectric constant materials while maintaining low leakage through selective operation of only non-defective elements.
Solution Approach 2:
The system changes the operational parameters by dynamically selecting which capacitors to include in the functional array based on their defect characteristics. Through programming and selective connection, the system adapts to the actual defect distribution in the ferroelectric material, optimizing the balance between capacitance density and leakage current.
2Quantity of substance
If large area capacitors are fabricated to increase capacitance, then capacitance is improved, but leakage current increases due to high defect density in ferroelectric materials
Solution Approach 1:
Instead of using a single large capacitor, the system employs multiple smaller capacitor elements arranged in an array. This segmentation allows the total capacitance to be achieved through parallel connection of multiple small capacitors, while defects are distributed across individual elements rather than affecting the entire large area, thereby reducing overall leakage current.
Solution Approach 2:
The system performs preliminary characterization and mapping of defect locations in the capacitor array during or after fabrication. This preliminary action enables subsequent programming to exclude defective capacitors before the device is put into service, ensuring that only non-defective capacitors contribute to the functional capacitance and minimizing leakage from the outset.
3Quantity of substance
If minimum dielectric thickness is used to increase capacitance, then capacitance density is improved, but dielectric rupture risk increases due to high electric field
Solution Approach 1:
The capacitor array is segmented into multiple individually addressable elements, allowing statistical selection of capacitors with higher quality dielectric layers. By selecting and using only the best-performing capacitors from the array, the system can operate at higher capacitance densities with thinner dielectrics while maintaining reliability through exclusion of marginally defective elements.
Solution Approach 2:
The system dynamically adjusts operational parameters including voltage levels and capacitor selection based on measured performance characteristics. This allows optimization of the capacitance-density-to-reliability tradeoff by operating each capacitor within its safe electric field limits while maximizing total array capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively identifies and excludes defective capacitors, reducing leakage current and enhancing the reliability and efficiency of capacitor arrays in semiconductor integrated circuits by selectively connecting only non-defective capacitors, thus improving the overall performance and longevity of the circuit.
Implementation Method 1
the capacitance C for a parallel plate capacitor as in FIG. 1, therefore, is determined by geometrical parameters A and d
Implementation Method 2
The crystalline silicon substrate is often highly doped with N-type or P-type impurities to reduce resistance
Data Source
AI summary
A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a plurality of circuit elements (322, 326, 330), and a plurality of transistors (320, 324, 328). Each transistor has a control terminal (314, 316, 318) and a current path coupled between the output terminal and a respective circuit element of the plurality of circuit elements. A control circuit (300) has a plurality of output terminals (314, 316, 318). Each output terminal is coupled to the control terminal of a respective transistor of the plurality of transistors. The control circuit produces control signals at respective output terminals to selectively turn off at least one transistor and turn on at least other transistors of the plurality of transistors at a first time.