Segmented Channel Layer Striation Reduction in Flash Memory
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Solution Overview
Problem
The striation phenomenon in channel layers of nonvolatile memory devices hinders the integrity and performance of vertically stacked cell transistors, which is a challenge in manufacturing high-integration flash memory devices.
Innovation Solution
A nonvolatile memory device design that includes a substrate with a channel layer protruding from it, surrounded by a gate conductive layer and a gate insulating layer, with specific insulating layers and air gaps to improve the structural integrity and reduce striation, along with a method of manufacturing involving sacrificial layers and spacer formation to create the desired structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked cell transistors are manufactured to achieve high integration, then device integration density is improved, but striation phenomenon in channel layer occurs which degrades channel integrity
Solution Approach 1:
The channel layer is segmented into multiple thinner layers (first channel layer and second channel layer) stacked vertically, with each layer having a thickness of 50-150nm. This segmentation prevents striation phenomenon that occurs in single thick channels while maintaining high vertical integration density for flash memory devices
Solution Approach 2:
The patent uses composite material structure where the channel layer is formed as a combination of multiple semiconductor layers with different compositions (e.g., Si-SiGe-Si structure). This composite approach improves channel integrity by reducing stress and preventing striation while enabling vertical stacking for high integration
2Ease of manufacture
If channel layer thickness is increased to reduce manufacturing complexity, then fabrication process is simplified, but striation phenomenon worsens degrading device performance
Solution Approach 1:
Instead of forming a single thick channel layer that is prone to striation, the channel is segmented into multiple thin layers (50-150nm each) stacked vertically. This segmentation maintains manufacturing feasibility through standard deposition processes while eliminating striation defects that plague thicker single-layer channels
Solution Approach 2:
The patent changes the thickness parameter of individual channel layers to 50-150nm, which is optimal for preventing striation phenomenon. This parameter optimization allows each thin layer to be formed without defects while the stacked configuration achieves the desired overall channel depth for high integration
Data Source
AI summary
A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.