Segmented Channel MOS Transistor with High-k Dielectric Isolation
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Solution Overview
Problem
Conventional MOSFET designs face challenges in scaling down to improve cost and performance, as techniques to reduce static power consumption, such as increasing channel doping and decreasing gate-dielectric thickness, often lead to decreased transistor performance by reducing on-current and increasing variability due to dimensional inconsistencies and geometrical irregularities.
Innovation Solution
The use of precisely-formed and regularly-spaced semiconductor material ridges connecting source and drain regions, with heavily doped sub-surface regions and high-permittivity dielectric materials, to form segmented channel regions that enhance performance consistency and reduce static power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate dielectric thickness is decreased to increase gate capacitance and control channel potential, then transistor performance is improved, but leakage current between gate electrode and channel region increases
Solution Approach 1:
The patent changes the dielectric constant parameter by introducing high-k dielectric materials (such as hafnium oxide, zirconium oxide, or tantalum oxide) with dielectric constants significantly higher than conventional silicon dioxide. This allows achieving the required gate capacitance with thicker dielectric layers, thereby reducing gate-to-channel leakage while maintaining effective gate control over the channel potential.
2Object-generated harmful factors
If channel dopant concentration is increased to suppress source-to-drain leakage current, then static power consumption is reduced, but carrier mobility is degraded and on-current decreases
Solution Approach 1:
The patent applies different dopant concentrations to different spatial regions within the channel. Specifically, higher dopant concentrations are applied near the source and drain regions to suppress leakage currents, while the central channel region maintains lower dopant concentration to preserve carrier mobility. This localized doping strategy allows simultaneous optimization of both leakage suppression and on-current performance.
Solution Approach 2:
The patent introduces lightly-doped extension regions (also called halo or pocket doping regions) as intermediary structures between the heavily-doped source/drain and the intrinsic channel. These extension regions with moderate dopant concentrations serve as transition zones that gradually modulate the electric field, thereby suppressing leakage currents while minimizing the adverse impact on carrier mobility in the main channel region.
3Object-generated harmful factors
If source and drain junction depths are decreased to suppress sub-surface leakage currents, then static power consumption is reduced, but parasitic series resistance increases and on-current decreases
Solution Approach 1:
The patent employs three-dimensional FinFET structures where the channel forms vertical fins extending from the substrate. This vertical dimension allows the gate to control the channel from multiple sides (front, back, and sidewalls), providing superior electrostatic control that effectively suppresses leakage currents. Simultaneously, the horizontal junction areas are maintained sufficiently large to ensure low parasitic series resistance, thus resolving the contradiction between leakage suppression and on-current maintenance.
4Productivity
If MOSFET dimensions are scaled down to improve cost and performance, then device density is increased, but device performance becomes highly sensitive to dimensional variation
Solution Approach 1:
The patent divides the channel into multiple segments by introducing sacrificial oxide layers or ridge structures that create distinct regions along the channel length. This segmentation allows independent optimization and control of different channel portions, reducing the impact of dimensional variations in any single region. The segmented structure also enables better stress management and more uniform electrical characteristics across the device, thereby improving performance consistency despite scaling-induced dimensional variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-performance MOSFETs with low static power consumption and reduced variability, achieving better on-current and consistency across devices by effectively managing source-to-drain leakage currents and stress within the channel region.
Implementation Method 1
The high-permittivity dielectric material increases the capacitive coupling between the gate electrode and the upper portion of the ridge sidewalls. Thus, the sides of the upper portions of the ridges can become conductive under the influence of gate
Implementation Method 2
Heavily doped sub-surface regions within the ridges serve to further reduce source-to-drain leakage currents
Data Source
AI summary
By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g. silicon-germanium, germanium, gallium arsenide, etc.), high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions to further enhance device performance.