Segmented Clip Structure for Low-Resistance Semiconductor Packaging
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Solution Overview
Problem
Conventional clip structures for packaged semiconductor devices have limited source contact area due to fabrication limitations, leading to increased package resistance and reduced performance, and require additional solder joints and smaller die sizes.
Innovation Solution
A clip structure with an integrally conductive leadframe and a gate wire bond that connects two die portions, allowing for a larger contact area and reducing package resistance by eliminating the need for a solder joint and optimizing the layout for increased contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional clip structure is used with a gate wire bond, then the gate bond pad opening size is limited to less than 200 um, but the source contact area is reduced and package resistance increases
Solution Approach 1:
The clip structure is divided into a first portion that integrally connects the source terminal with the first die portion, and a second portion that connects to the gate terminal. This segmentation allows the source contact area to be maximized while the gate connection is handled separately through a wire bond, resolving the contradiction between contact area and bond pad size limitations.
Solution Approach 2:
A wire bond is introduced as an intermediary element to connect the second portion of the clip structure with the second die portion. This intermediary allows the gate connection to be made without requiring a large bond pad opening on the first die portion, thereby maximizing the source contact area while maintaining reliable electrical connection.
2Area of moving object
If a conventional clip structure with additional solder joint is used, then the lead design is more complex, but the die size is reduced resulting in smaller source clip contact area
Solution Approach 1:
The first portion of the clip structure integrates both the source terminal connection and the support function into a single integral structure. This merging eliminates the need for separate solder joints at the lead while maximizing the source clip contact area, thereby reducing device complexity while improving electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces overall package resistance and improves performance by maximizing the contact area between die portions, enabling better electrical conductivity and heat management.
Implementation Method 1
The gate wire bond (which may also be called an interconnect) is configured to connect the second portion with the second die portion
Implementation Method 2
The first portion is electrically conductive, and the first portion is configured to integrally connect a source terminal with the first die portion
Implementation Method 3
the leadframe is a conductive heatslug configured to connect to the die of the packaged semiconductor device via a conductive die attach adhesive material, e.g. solder
Data Source
Figure 1~2
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AI summary
A clip structure for a packaged semiconductor device. The packaged semiconductor device comprises a first die portion and a second die portion being electrically isolated from the first die portion. The clip structure comprises a first portion, a second portion and a gate wire bond. The first portion is electrically conductive, and the first portion is configured to integrally connect a source terminal with the first die portion. The second portion is electrically conductive and is electrically isolated from the first portion, and is configured to connect to a gate terminal. The gate wire bond is configured to connect the second portion with the second die portion.