Segmented Semiconductor Clip Structure for Lower Package Resistance
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Solution Overview
Problem
Conventional clip structures for packaged semiconductor devices have limited source contact area due to fabrication limitations, leading to increased package resistance and reduced performance, and require additional solder joints and smaller die sizes.
Innovation Solution
A clip structure with an integrally conductive leadframe and a gate wire bond that connects two die portions, allowing for a larger contact area and reducing package resistance by eliminating the need for a solder joint and optimizing the layout for increased contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional clip structure with stamp clip fabrication is used, then the gate bond pad opening can be made larger than 500 um, but the source contact area is limited and package resistance increases
Solution Approach 1:
The clip structure is segmented into a gate clip portion and a source clip portion that are electrically isolated from each other. The gate clip connects to the gate bond pad opening while the source clip connects to the source bond pad, allowing independent optimization of each contact area without interference between gate and source connections.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the gate clip and source clip, enabling them to be physically close while maintaining electrical isolation. This allows the source contact area to be maximized without being constrained by gate connection requirements.
2Area of moving object
If wire bond is used for gate connection instead of stamp clip, then the bond pad size can be reduced to less than 200 um, but the gate clip interconnector cannot be made larger than 500 um due to fabrication limitations
Solution Approach 1:
The mechanical stamp clip fabrication process is replaced with a wire bonding process for the gate clip interconnector. This substitution eliminates the 500 um fabrication limitation and allows precise control of the gate bond pad opening size while maintaining ease of manufacture through established wire bonding techniques.
3Reliability
If additional solder joint is added at the lead to improve connection, then the reliability improves, but the device complexity and manufacturing steps increase
Solution Approach 1:
The clip structure integrates both gate and source connections into a single unified component that attaches to the die in one operation. The gate clip and source clip are formed as integral parts of the same structure, eliminating the need for separate solder joints at the lead and reducing manufacturing complexity while maintaining reliable electrical connections.
4Area of stationary object
If smaller die size is used to reduce package area, then the package footprint is reduced, but the source clip contact area decreases due to more area being needed for lead design
Solution Approach 1:
The clip structure utilizes three-dimensional positioning and layering to maximize contact area within a compact footprint. The gate clip and source clip are arranged in different spatial planes and orientations, allowing optimal use of available space and enabling large contact areas without increasing the overall package footprint.
Data Source
AI summary
A clip structure for a packaged semiconductor device is provided. The packaged semiconductor device includes a first die portion and a second die portion being electrically isolated from the first die portion. The clip structure includes a first portion, a second portion and a gate wire bond. The first portion is electrically conductive, and the first portion is configured to integrally connect a source terminal with the first die portion. The second portion is electrically conductive and is electrically isolated from the first portion and is configured to connect to a gate terminal. The gate wire bond is configured to connect the second portion with the second die portion.