Segmented CNN Hardware Accelerator Kernel Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CNN hardware accelerators face challenges in configurability, flexibility, and computational efficiency due to mismatches in computation throughput and memory bandwidth, which hinder their deployment in embedded environments and limit their ability to process various CNN configurations efficiently.
Innovation Solution
A modular, segmented, and reconfigurable hardware accelerator is designed with modified kernel structures, allowing multiple smaller kernels to be run concurrently and utilizing pixel and weight loading units to mitigate latency and enhance convolution processing speed, along with a controller to manage these units efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CNN hardware accelerators use fixed kernel structures and processing elements, then computation throughput is improved, but configurability and flexibility deteriorate
Solution Approach 1:
The kernel structure is segmented into multiple smaller sub-kernels that can be independently configured and executed. Instead of using a single fixed kernel size, the system divides the convolution operation into multiple smaller kernel applications, allowing flexible adaptation to different CNN configurations while maintaining high throughput through parallel execution of these segmented operations.
Solution Approach 2:
The hardware accelerator employs dynamic reconfiguration capabilities where the kernel structure and processing elements can be adaptively adjusted based on the specific CNN configuration requirements. This dynamic nature allows the system to optimize for different kernel sizes, strides, and padding values without being locked into a fixed architecture, thereby maintaining both high throughput and configurability.
2Productivity
If hardware accelerators increase processing elements and computation units, then computational efficiency is improved, but power consumption and resource requirements worsen
Solution Approach 1:
Instead of deploying a large number of processing elements simultaneously, the system uses a smaller set of processing elements that are dynamically reused across multiple kernel operations. By partially utilizing the computational resources across time through the segmented kernel approach, the system achieves high computational efficiency without the excessive power consumption that would result from having all processing elements active at once.
Solution Approach 2:
The segmented kernel structure enables continuous utilization of the processing elements by pipelineing the execution of multiple sub-kernels. While one sub-kernel is being processed, the system prepares the next sub-kernel, ensuring that the processing elements remain continuously engaged in useful computation without idle cycles, thereby maintaining high efficiency with reduced resource requirements.
3Productivity
If CNN hardware accelerators use larger kernel sizes, then processing capability is improved, but memory bandwidth requirements and latency worsen
Solution Approach 1:
Large kernel operations are segmented into multiple smaller sub-kernel applications. Instead of loading and processing a single large kernel that would require extensive memory bandwidth and time, the system divides the large kernel operation into multiple smaller sub-kernels that can be processed in sequence or parallel, reducing the memory bandwidth requirement for each operation and decreasing overall latency through efficient resource utilization.
Data Source
AI summary
An accelerator with a modified kernel design for convolution processing in a Convolutional Neural Network (CNN) model is disclosed wherein the convolution execution time is reduced. A kernel structure is disclosed in the embodiment for the convolution operations that improves the overall performance of a CNN. Further, two loading units for weight and pixel loading reduce the latency involved in loading the network parameters into the processing elements. Moreover, a controller has been designed and included in the system architecture to aid the functioning of loading units efficiently.