Segmented Collector Stacked NPN for ESD Clamp Integration
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Solution Overview
Problem
Integrated circuits face challenges in achieving low resistance, uniform current distribution, and consistent breakdown voltage during electrostatic discharge events, particularly with advanced CMOS transistors, making it difficult to integrate effective clamp circuits without additional process steps.
Innovation Solution
The integration of a stacked bipolar transistor pair with segmented collectors and emitters, where the upper collector is divided into segments on both sides of the lower NPN and the lower emitter is segmented to prevent current crowding, reducing resistance and improving current uniformity, while being formed concurrently with other circuit elements to minimize process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a clamp circuit is integrated in advanced CMOS transistors, then the circuit area is reduced, but achieving low resistance and uniform current distribution becomes difficult
Solution Approach 1:
The upper collector is divided into multiple collector segments (e.g., four segments) separated by collector separators. This segmentation distributes the current flow paths uniformly across the structure, preventing current crowding and achieving uniform current distribution while maintaining a compact integrated area.
Solution Approach 2:
Different regions of the clamp circuit are assigned different doping concentrations and geometries. The collector segments have optimized doping levels, the base has specific doping profiles, and the emitter has segmented structure with varying dimensions. This local optimization ensures low resistance in critical paths while maintaining current uniformity across the entire structure.
2Area of stationary object
If a clamp circuit is integrated in advanced CMOS transistors, then the circuit area is reduced, but achieving low resistance becomes difficult
Solution Approach 1:
The lower emitter is divided into multiple emitter segments (e.g., four segments) separated by emitter separators. This segmentation creates multiple parallel current flow paths from the emitter to the base, effectively reducing the total resistance while maintaining a compact footprint suitable for integration.
Solution Approach 2:
The stacked NPN transistor pair is vertically integrated with shared structures. The base of the upper NPN shares the base region of the lower NPN, and the collector of the lower NPN serves as the emitter for the upper NPN. This merging of structures reduces the overall area while providing multiple parallel conduction paths for low resistance.
3Reliability
If additional process steps are introduced to improve clamp circuit performance, then resistance and current uniformity improve, but manufacturing complexity increases
Solution Approach 1:
The clamp circuit structures are formed concurrently with other circuit elements using shared process steps. The doped regions for the stacked NPN transistors are created using the same ion implantation or diffusion processes as other bipolar devices in the circuit. Collector and emitter separators are formed using the same isolation processes as other circuit elements, eliminating the need for additional dedicated process steps.
Solution Approach 2:
The segmented collector and emitter structures serve multiple functions: they provide current uniformity, reduce resistance, and can be formed using standard bipolar transistor fabrication processes. The same doping and isolation techniques used for regular bipolar transistors are applied to the clamp circuit, making the manufacturing process universal across different circuit types.
Data Source
AI summary
An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.