Segmented Column Selection Lines for Faster Memory Arrays
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Solution Overview
Problem
The increasing size of memory banks in semiconductor devices leads to increased line loading, which degrades data transmitting speed, necessitating a performance improvement in memory devices.
Innovation Solution
A semiconductor memory device with a memory cell array divided into blocks, utilizing a control logic circuit to generate address signals and repeater selection signals, and employing bit line sense amplifiers and column selection lines to enhance data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of memory bank is increased to improve integration, then the integration is improved, but the line loading is increased which degrades data transmitting speed
Solution Approach 1:
The memory bank is divided into multiple sub-banks, and each column selection line is segmented into multiple sections with repeaters inserted at intermediate points. This segmentation reduces the effective length of signal transmission paths, lowering line loading and maintaining data transmitting speed while allowing the overall memory bank size to increase for improved integration.
Solution Approach 2:
Repeaters are introduced as intermediary components along the column selection lines. These repeaters actively regenerate and retransmit signals, acting as mediators that compensate for signal degradation over long transmission distances. This enables the memory bank to be scaled up without proportionally increasing line loading, thus maintaining high data transmitting speed while improving integration.
2Productivity
If the size of memory bank is increased to improve integration, then the integration is improved, but the power consumption is increased
Solution Approach 1:
The column selection lines are segmented into multiple sections with repeaters positioned at strategic points. This segmentation allows the memory bank to be divided into smaller operational units that can be activated independently, reducing the overall power consumption while maintaining high integration through the expanded memory bank structure.
Solution Approach 2:
Instead of activating the entire memory bank simultaneously, the invention enables partial activation of specific sub-banks and column selection line sections based on actual data access requirements. This partial action approach reduces power consumption by keeping only necessary portions of the memory bank active, while the overall integrated structure remains available for high-capacity operations when needed.
Data Source
AI summary
A memory device includes a memory cell array which includes a plurality of word lines and a plurality of bit lines; a plurality of column selection lines which extends over the memory cell array and includes a first part of the memory cell array and a second part connected to the first part; a plurality of bit line sense amplifiers each connected to a bit line and configured to sense data stored in a memory cell; a plurality of local sense amplifiers each configured to output the sensed data from one of the bit line sense amplifiers through a column selection transistor connected to a local column selection line; a control logic circuit which generates a row address signal indicating an activation word line and a column address signal indicating an activation bit line; and a column decoder which activates a column selection line based on the column address signal.