Segmented Conductive Lines Double Patterning
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Solution Overview
Problem
Double patterning techniques in semiconductor fabrication face challenges with shorts and misalignment, especially in designs with meandering patterns, due to optical proximity correction reintroducing minimum pitch and gap sizes, leading to reduced yield and circuit reliability.
Innovation Solution
The implementation of novel double patterning methods where stitching bridges are formed in an adjacent material layer, acting as local interconnects for segmented conductive lines, allowing for less aggressive optical proximity correction and avoiding the re-introduction of minimum pitch or gap, thus maintaining a minimal cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction (OPC) is used to improve pattern transfer in double patterning, then pattern transfer accuracy is improved, but minimum pitch and gap sizes are reintroduced causing shorts and misalignment
Solution Approach 1:
The conductive lines are divided into two separate layouts (first and second layouts) with alternating lines, allowing each to be patterned independently with relaxed pitch requirements. This segmentation eliminates the need for aggressive OPC while maintaining pattern fidelity and avoiding shorts.
Solution Approach 2:
The invention transitions from a single-layer patterning approach to a multi-layer approach where conductive lines are distributed across different material layers. By forming some conductive lines in a first material layer and others in a second material layer, the patent avoids the pitch and gap limitations of single-layer OPC.
2Length of moving object
If double patterning is used to print small minimum feature sizes, then feature size reduction is achieved, but shorts and misalignment occur in meandering patterns
Solution Approach 1:
The design is segmented into two separate layouts where alternating conductive lines are assigned to different layers. This allows each layer to be patterned with relaxed alignment tolerances, eliminating the misalignment problems that occur when trying to pattern all lines in a single layer with aggressive OPC.
Solution Approach 2:
The patent introduces an intermediate step of creating a first layout and second layout with alternating lines before final patterning. This intermediary segmentation acts as a mediator that resolves the conflict between small feature sizes and alignment precision by distributing the patterning burden across multiple layers.
3Manufacturing precision
If aggressive optical proximity correction is applied to maintain minimum pitch, then pattern fidelity is improved, but weak lithography spots are created increasing short risk
Solution Approach 1:
By segmenting the conductive lines into alternating patterns across two layouts, the patent eliminates the need for aggressive OPC that creates weak lithography spots. Each layout can be patterned with standard OPC, maintaining pattern fidelity without creating reliability issues.
Data Source
AI summary
Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.